A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks

Abstract

Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Network-on-Chip (NoC) architectures are required to not only provide ultra-low latency, but also occupy a small footprint and consume as little energy as possible. Further, reliability is rapidly becoming a major challenge in deep sub-micron technologies due to the increased prominence of permanent faults resulting from accelerated aging effects and manufacturing/testing challenges.Towards the goal of designing low-latency, energyefficient and reliable on-chip communication networks, we propose a novel fine-grained modular router architecture. The proposed architecture employs decoupled parallel arbiters and uses smaller crossbars for row and column connections to reduce output port contention probabilities as compared to existing designs. Furthermore, the router employs a new switch allocation technique known as "Mirroring Effect" to reduce arbitration depth and increase concurrency. In addition, the modular design permits graceful degradation of the network in the event of permanent faults and also helps to reduce the dynamic power consumption. Our simulation results indicate that in an 8 × 8 mesh network, the proposed architecture reduces packet latency by 4-40% and power consumption by 6-20% as compared to two existing router architectures. Evaluation using a combined performance, energy and fault-tolerance metric indicates that the proposed architecture provides 35-50% overall improvement compared to the two earlier routers.

Impact of Predictive Switching in 2-D Torus Networks

“…Path-sensitive router [12] and Guide flit queuing [13] embed a VC identifier in the packet header for the next router. Destination-based head-of-line blocking elimination also manages input buffers associated with packet destination groups [15].…”

A Virtual Channel Allocation Algorithm for NoC

“…The benefits of NoC are attractive, but attaining their full potential will present lots of challenges among which power consumption stands out as one of the most critical challenges [5] . Since router is one of the kernel components of NoC and it has significant influence on both the performance and power consumption of NoC [6] , we mainly focus on it in this paper. A typical virtual channel router structure is shown in Figure.1.…”

Floorplan-Aware High Performance NoC Design

“…Jongman Kim et al reuse the decoupling concept to design a low-latency switch [53,54]. In [53], the Row-Column (RoCo) switch is presented.…”

“…In [53], the Row-Column (RoCo) switch is presented. This switch achieves low latency decomposing a 2D switch into two halves, one in each dimension.…”

“…Some of these modify switch pipelining shown in Figure 3.1(b) by performing some stages in parallel. In contrast, other proposals modify the whole switch architecture [44,50,53]. In general, switch optimization efforts lie on improving switch performance measured as throughput or latency at the expense of increasing the complexity of the switch.…”