Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA 2007) 2007

DOI: 10.1109/iwia.2007.8

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Impact of Predictive Switching in 2-D Torus Networks

Tsutomu Yoshinaga

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,

Hitoshi Murakami

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,

Michihiro Koibuchi

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Abstract: Abstract

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Cited by 4 publications

References 19 publications

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Prediction router: Yet another low latency on-chip router architecture

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et al. 2009

2009 IEEE 15th International Symposium on High Performance Computer Architecture

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Prediction router: Yet another low latency on-chip router architecture

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,

²

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³

et al. 2009

2009 IEEE 15th International Symposium on High Performance Computer Architecture

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No abstract

An Efficient Path Setup for a Photonic Network-on-Chip

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et al. 2010

2010 First International Conference on Networking and Computing

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Electrical Network-on-Chip (NoC) faces critical challenges in meeting the high performance and low power consumption requirements for future multicore processors interconnection. Recent tremendous advances in CMOS compatible optical components give the potential for photonics to deliver an efficient NoC performance at an acceptable energy cost. However, the lack of in flight processing and buffering of optical data made the realization of a fully optical NoC complicated. A hybrid architecture which uses optical high bandwidth transfer and a tiny electrical control network can take advantage of both interconnection methods to offer an efficient performance-per-watt infrastructure to connect multicore processors and System-on-Chip (SoC). In this paper, we propose a hybrid photonic torus NoC (HPNoC) that uses a predictive switching to improve the performance of a hybrid architecture. By using prediction techniques, we can reduce the path set up latency for the electrical control network hence improving the overall end-to-end delay for communication in the HPNoC. Simulation results using a cycle accurate simulator under uniform, neighbor and bitreversal traffic patterns for 64 nodes show that predictive switching considerably improves the HPNoC overall performance.

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

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et al. 2011

IEEE Trans. Comput.

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