Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu; Yoshinaga, Tsutomu

doi:10.1109/tc.2011.17

Cited by 24 publications

(22 citation statements)

References 28 publications

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“…The hardware area of the electrical network is increased by 4.8-12.0% as reported in our previous work [7]. Prediction routers speculatively forward the packets inside a router bypassing some pipeline stages.…”

Section: Predictive Switching Based Path Setupmentioning

confidence: 77%

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

Adi

Matsutani

Koibuchi

et al. 2011

IJNC

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Electrical network-on-chip (NoC) faces critical challenges in meeting the high performance and low power consumption requirements for future multicore processors interconnection. Re- 244International Journal of Networking and Computing cent tremendous advances in CMOS compatible optical components give the potential for photonics to deliver an efficient NoC performance at an acceptable energy cost. However, the lack of in flight processing and buffering of optical data made the realization of a fully optical NoC complicated. A hybrid architecture which uses optical high bandwidth transfer and an electrical control network can take advantage of both interconnection methods to offer an efficient performance-per-watt infrastructure to connect multicore processors and system-on-chip (SoC). In this paper, we propose a predictive switching and a reservation based path setup techniques to reduce the path setup latency of such hybrid photonic network-on-chip (HPNoC). By using these techniques, it is possible to reduce the latency for end-to-end communication in a HPNoC improving its overall performance. In the simulation, we use a cycle accurate simulator under uniform, neighbor, and bitreversal traffic patterns for a 64-node torus topology. The results show that the proposed techniques considerably improve the overall latency of HPNoC.

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Section: Predictive Switching Based Path Setupmentioning

confidence: 77%

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

Adi

Matsutani

Koibuchi

et al. 2011

IJNC

Self Cite

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“…PR [4] is an advanced router design whose speculative switch traversal is enabled with predictions of the output ports before a packet actually comes to a router. If a predictive routing succeeds, the latency of the router pipeline is hidden since they are already carried out with a predicted route computation result.…”

Section: The Noc Optimization Techniques and Their Impactsmentioning

confidence: 99%

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

Kondo

Nakada

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYNetworks-on-Chip (or NoCs, for short) play important roles in modern and future multi-core processors as they are highly related to both performance and power consumption of the entire chip. Up to date, many optimization techniques have been developed to improve NoC's bandwidth, latency and power consumption. But a clear answer to how energy efficiency is affected with these optimization techniques is yet to be found since each of these optimization techniques comes with its own benefits and overheads while there are also too many of them. Thus, here comes the problem of when and how such optimization techniques should be applied. In order to solve this problem, we build a runtime framework to throttle these optimization techniques based on concise performance and energy models. With the help of this framework, we can successfully establish adaptive selections over multiple optimization techniques to further improve performance or energy efficiency of the network at runtime.

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“…[1,2,3], which complicates the router significantly. Matsutani et al proposed predictions router which predicts the outport to be used by the next packet, and if the prediction hits, the next packet can be transferred without waiting for the routing computation and switch arbitration [4]. Pseudo-circuit is proposed to reduce the per-hop latency by reusing the switch connection of departing packet [5].…”

Section: Introductionmentioning

confidence: 99%

Self-selection pseudo- circuit: a clever crossbar pre-allocation

Liu

et al. 2012

IEICE Electron. Express

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Abstract:This paper proposes self-selection pseudo-circuit (SP), a simple and effective approach to increase switch connection reusing rate and improve the network performance. It especially suits the network in which the performance is dominated by the number of hops. In SP scheme, multiple switch connections are allowed to be reserved for one inport, and the flit can reuse the partial switch connection(s) based on the routing information. For the evaluation with the traces from Splash-2, SP reduces the interconnection latency by up to 21.6% (16.9% average) with 16-core CMP configuration, and 22.2% (19.5 on average) with 64-core CMP configuration. Evaluated with synthetic traffic, the proposed scheme decreases the latency up to 19% (16% average).

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Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

Cited by 24 publications

References 28 publications

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

Self-selection pseudo- circuit: a clever crossbar pre-allocation

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