An Efficient Path Setup for a Photonic Network-on-Chip

Abstract

Electrical Network-on-Chip (NoC) faces critical challenges in meeting the high performance and low power consumption requirements for future multicore processors interconnection. Recent tremendous advances in CMOS compatible optical components give the potential for photonics to deliver an efficient NoC performance at an acceptable energy cost. However, the lack of in flight processing and buffering of optical data made the realization of a fully optical NoC complicated. A hybrid architecture which uses optical high bandwidth transfer and a tiny electrical control network can take advantage of both interconnection methods to offer an efficient performance-per-watt infrastructure to connect multicore processors and System-on-Chip (SoC). In this paper, we propose a hybrid photonic torus NoC (HPNoC) that uses a predictive switching to improve the performance of a hybrid architecture. By using prediction techniques, we can reduce the path set up latency for the electrical control network hence improving the overall end-to-end delay for communication in the HPNoC. Simulation results using a cycle accurate simulator under uniform, neighbor and bitreversal traffic patterns for 64 nodes show that predictive switching considerably improves the HPNoC overall performance.

Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems

“…Petracca et al [48] proposed a non-blocking torus hybrid-PNoC where the conventional path setup scheme is used. Cisse et al [10] proposed a hybrid-PNoC torus named HPNoC which uses predictive switching [36] in the ECN to reduce the setup latency by reducing the pipeline stages of the electrical router. Although the latency is reduced by using such predictive switching, the path setup steps are all generated and transmitted in the ECN.…”

“…This process is repeated until the Tear-down reaches the destination and all optical resources are released. It is important to mention that the path-setup and path-blocked processes of the proposed algorithm are very similar to the conventional ones[4,20,10,32,33,35]. The main difference is that the MRST in our proposal contains only two states: Free and Active.…”

“…In conventional hybrid PNoC systems [4,10,33,42,48,36,37,38,9], the source node first issues a configuration packet via a copper-based electrical link to the destination node. The configuration packet is routed via an Electric Control Network (ECN), reserving the photonic switches along the path for the photonic message which will follow it in the Photonic Communication Network (PCN).…”

An Energy-Efficient High-Throughput Mesh-Based Photonic On-Chip Interconnect for Many-Core Systems

“…Photonic Network-on-Chip (PNoC) [1][2][3][4][5][6][7] is a novel concept enabling ultra-high communication throughput in the terabits per second range, low power and low communication latency. When powered with a wavelength division multiplexing (WDM) scheme, multiple parallel optical streams of data are concurrently transferred through a single on-chip waveguide.…”

“…Using Dense Wavelength Division Multiplexing (DWDM), up to 64 (and theoretically more) separate wavelengths can be multiplexed into a light stream transmitted on a single waveguide [16]. In conventional hybrid PNoC systems [1,3,5,[17][18][19][20], the source node first issues a path configuration packet, which includes destination address information and other additional control information, via a copper-based electrical link. The configuration packet is routed via an Electric Control Network (ECN), reserving the photonic switches and channels along the path for the photonic message.…”