A hardware efficient direct digital frequency synthesizer

Curticapean, F.; Niittylahti, J.

doi:10.1109/icecs.2001.957664

Cited by 29 publications

(6 citation statements)

References 11 publications

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“…The errors corresponding to the approximations in left and right terms of (6) are given respectively by (7) M must be chosen by considering the amplitude resolution, i.e. the number of bits (Q) which is used for quantizing a sine sample.…”

Section: Proposed Algorithmmentioning

confidence: 99%

“…Hence, many ROM compression techniques to reduce the storage requirements have been proposed. Architectures based on trigonometric approximation which use the trigonometric identities of the sine function have been proposed to reduce the number of phase bits (w) addressing the ROM [5]- [7] and will be described briefly in the section 2. Linear and Polynomial interpolation architectures have been employed for high-performance DDFS as well [8]- [10].…”

Section: Introductionmentioning

confidence: 99%

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A Novel DDFS Based on Trigonometric Approximation with a Scaling Block

Babak

Keshavarzi

2009

2009 Sixth International Conference on Information Technology: New Generations

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Attempts have been made to present a 32bit direct digital frequency synthesizer (DDFS) with a new ROM compression method based on the trigonometric identities of the sine function. In our proposed DDFS architecture 128 sinusoidal samples (1664 bits) are stored in the ROM and the other samples between these consecutive samples are obtained by using a 7×7 multiplier and a scaling block. This architecture was simulated at the system level by MATLAB Simulink and the results were mentioned. By using this algorithm, a very high compression ratio (551.3:1) and the spurious free dynamic range (SFDR) of 85dbc are resulted.Key Words: compression ratio, phase to sineamplitude conversion, quadrant phase, quarter symmetry, spurious free dynamic range (SFDR).

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Section: Proposed Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Novel DDFS Based on Trigonometric Approximation with a Scaling Block

Babak

Keshavarzi

2009

2009 Sixth International Conference on Information Technology: New Generations

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“…Based on the stored sample 'sin(x)' and the slope 'sin(π/2-x)', the sine value of object phase 'x+delta' can be calculated according to (1). We also observe that the slope does not need to be stored, because the slope of one sample 'sin(x)' is just the value of another sample 'sin(π/2-x)' if samples are evenly distributed in phase range of 0~π/2.…”

Section: Basic Idea 21 Algorithmmentioning

confidence: 99%

A simple DDS architecture with highly efficient sine function lookup table

Wang

Chang

Chou

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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“…Bellaouar proposes the architecture based on linear interpolation where the ROM size increases in proportional with inverse square root of the SFDR [5]. Using the sine-phase difference Niittylahti et al [6] proposes ROM reduced architecture for the DDFS. Another work by F. Babak et al [7] compressed the ROM size by 551.3:1 using trigonometric approximation with a scaling block.…”

Section: Introductionmentioning

confidence: 99%

A novel low-latency, high-speed DDFS architecture

Hatai

Chakrabarti

2010

2010 Annual IEEE India Conference (INDICON)

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A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency (requires 11 clock cycles) pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of u 4 1.5 10 . The FPGA implementation of the proposed design has an SFDR of -94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion..

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A hardware efficient direct digital frequency synthesizer

Cited by 29 publications

References 11 publications

A Novel DDFS Based on Trigonometric Approximation with a Scaling Block

A Novel DDFS Based on Trigonometric Approximation with a Scaling Block

A simple DDS architecture with highly efficient sine function lookup table

A novel low-latency, high-speed DDFS architecture

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