A Hardware Packet Re-Sequencer Unit for Network Processors

Scaling multi-core network processors without the reordering bottleneck

“…However, it results in an insufficient utilization of the cores, and therefore in a lower throughput, due to the fact that several elephant flows may map to the same core [16]. Moreover, it is possible to adapt the load-balancing scheme by using feedback on the core utilization in order to increase throughput [17], [18].…”

“…In particular, those flows can be sent to other ordering domains by hashing the packet header as in [16]. This type of ordering domain can coexist in parallel with our processing-based reordering domains.…”

“…A second, ideal approach is to rely on per-flow sequencing [21]- [23], thus providing a minimal reordering delay. However, as explained in [16], it is not scalable to a large number of network flows because of the large number of needed counters. A third method to avoid packet reordering is to keep an inter-thread signaling system between the cores [20].…”

“…Therefore, each arriving packet can be allocated to any arbitrary PE for processing. As commonly assumed, we consider a single stream of incoming packets [16], [22]- [25]. We allow arbitrary arrival times of the packets, and assume infinite buffer sizes.…”

“…A fourth and last appealing approach is to statically aggregate flows by hashing the flow identifier in the packet header into several ordering domains [16]. A different sequence number generator is then assigned for each ordering number.…”