An Application-Aware Load Balancing Strategy for Network Processors

Ohlendorf, Rainer; Meitinger, Michael; Wild, Thomas; Herkersdorf, Andreas

doi:10.1007/978-3-642-11515-8_13

Cited by 5 publications

(2 citation statements)

References 7 publications

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“…High load and absence of data locality could lead to a performance degradation in AF methods. Ohlendorf et al [15] explored load balancing strategies to optimize the NP performance in consideration of QoS requirements and CPU utilization. A combination scheme of packet scheduler and flow scheduler for various application types was proposed.…”

Section: Related Workmentioning

confidence: 99%

Protocol-Aware Packet Scheduling Algorithm for Multi-Protocol Processing in Multi-Core MPL Architecture

Zhang

Wang

Sheng

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYCache affinity has been proved to have great impact on the performance of packet processing applications on multi-core platforms. Flow-based packet scheduling can make the best of data cache affinity with flow associated data and context structures. However, little work on packet scheduling algorithms has been conducted when it comes to instruction cache (I-Cache) affinity in modified pipelining (MPL) architecture for multi-core systems. In this paper, we propose a protocol-aware packet scheduling (PAPS) algorithm aiming at maximizing I-Cache affinity at protocol dependent stages in MPL architecture for multi-protocol processing (MPP) scenario. The characteristics of applications in MPL are analyzed and a mapping model is introduced to illustrate the procedure of MPP. Besides, a stage processing time model for MPL is presented based on the analysis of multi-core cache hierarchy. PAPS is a kind of flowbased packet scheduling algorithm and it schedules flows in consideration of both application-level protocol of flows and load balancing. Experiments demonstrate that PAPS outperforms the Round Robin algorithm and the HRW-based (HRW) algorithm for MPP applications. In particular, PAPS can eliminate all I-Cache misses at protocol dependent stage and reduce the average CPU cycle consumption per packet by more than 10% in comparison with HRW.

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Section: Related Workmentioning

confidence: 99%

Protocol-Aware Packet Scheduling Algorithm for Multi-Protocol Processing in Multi-Core MPL Architecture

Zhang

Wang

Sheng

et al. 2017

IEICE Trans. Inf. & Syst.

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“…Once a decision has been made the input packets are enqueued into the input queue of the target core. The queue size is set to 32 packet descriptors for each queue based on previous research [32]. A packet is lost when it is assigned to a queue which is already full.…”

Section: ) Schedulermentioning

confidence: 99%

Flow Migration on Multicore Network Processors: Load Balancing While Minimizing Packet Reordering

Iqbal

Holt²,

Ryoo

et al. 2013

2013 42nd International Conference on Parallel Processing

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Abstract-With ever increasing network traffic rates, multicore architectures for network processors have successfully provided performance improvements through high parallelism. However, naively allocating the network traffic to multiple cores without considering diversified application nature and flow locality results in issues such as packet reordering, load imbalance and inefficient cache usage. Consequently, these issues degrade the performance of latency sensitive network processors by dropping packets or delivering packets out of order. In this paper, we propose a packet scheduling scheme that considers the multiple dimensions of locality to improve the throughput of a network processor while minimizing out of order packets. Our scheduling policy tries to maintain packet order by maintaining the flow locality, minimizes the migration of flows from one core to another by identifying the aggressive flows, and partitions the cores among multiple services to gain instruction cache locality. The scheduler uses a novel low cost two-level caching scheme to identify top aggressive flows. Our light weight hardware implementation shows improvement of 60% in the number of packets dropped and 80% improvement in the out-of-order packet deliveries over previously proposed techniques.

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Multiprocessor System-on-Chip

Hübner¹,

Becker²

2011

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An Application-Aware Load Balancing Strategy for Network Processors

Cited by 5 publications

References 7 publications

Protocol-Aware Packet Scheduling Algorithm for Multi-Protocol Processing in Multi-Core MPL Architecture

Protocol-Aware Packet Scheduling Algorithm for Multi-Protocol Processing in Multi-Core MPL Architecture

Flow Migration on Multicore Network Processors: Load Balancing While Minimizing Packet Reordering

Multiprocessor System-on-Chip

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