A $\hbox{Gb/s}+$ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time

Abstract

This brief introduces a low-noise slew-rate/ impedance-controlled high-speed output driver in 0.18-μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.1-3.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and −1.30%, respectively.Index Terms-Electromagnetic interference (EMI), fast compensation, low power, process, voltage, and temperature (PVT) variation detection, slew rate.

2 × VDD output buffer with 36.4% slew rate improvement using leakage current compensation

“…Kwak et al [1] reported 2000 MHz data rate and 2.1–3.58 V/ns SR. However, it provides only one output voltage mode.…”

“…Introduction: Mixed-voltage output buffers are often required to operate given different supply voltages. To attain transmission quality in extreme environments, the slew rate (SR) was reported to be selfadjusted using phase-locked loop, delay-locked loop, speed-locked loop based and PVT (process, voltage, and temperature) [1,2] compensation for the output buffers to meet different standards, e.g. low-power double-data-rate two (LPDDR2) (1.0-2.5 V/ns), and peripheral components interconnect X (PCI-X) 133 (1-4 V/ns).…”

“…However, it does not provide the leakage current compensation and the data rate is still slow. Kwak et al [1] reported 2000 MHz data rate and 2.1-3.58 V/ns SR. However, it provides only one output voltage mode.…”

A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique

“…[4][5][6] dedicating to I/Os between different voltage domains, for example, chip-to-chip I/Os between 0.9 and 1.8 V supply, limit the maximum speed of the drivers due to the introduction of extra loading by the feedback paths. To avoid the closed-loop SR detection and control, an open-loop SR control is preferred [7][8][9][10][11][12][13], which usually employs an independent PVT detector to control the SR of the driver without any extra loading at the output node. A SR output driver for the ultra direct memory access (UDMA100) is introduced in ref.…”

“…[8], delayed versions of the signal summed at the output of a transmitter using conventional segmented voltage‐mode Complementary Metal Oxide Semiconductor (CMOS) driver exhibit large PVT variations, and thus may cause very sharp glitches at the rising and falling edges. A PVT detector can be used to obtain the adaptive control signal of the segmented driver [9]. Nevertheless, this approach requires careful tuning of the driver as well, and the resolution of PVT compensation is limited by the number of bits in the PVT detector.…”