A heterogeneous digital signal processor implementation for dynamically reconfigurable computing

Rossi, Davide; Campi, Fabio; Deledda, A.; Spolzino, S.; Pucillo, S.

doi:10.1109/cicc.2009.5280747

Cited by 8 publications

(4 citation statements)

References 7 publications

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“…It is interesting to notice that while DSP instructions do not improve the performance of the core during execution of the smart trigger kernel, its implementation on the IPA provides even more benefits with respect to the data-flow part of the application (motion detection), improving performance by 10x with respect to execution on the processor (Table V). C. Comparison with the state of the art architectures Table VI presents the performance comparison of the smart visual trigger application running on a CPU and two state of the art reconfigurable array architectures [7] [8], chosen due to the availability of the target application, with similar features to other state of the art CGRAs. Results show that, although the two state of the art CGRAs deliver huge performance when dealing with the data-flow portion of the application, thanks to highly optimized and pipelined datapath that allows to implement operations on binary images as boolean operations [7], they are not able to implement the control dominated kernel, which runs on the CPU forming a major bottleneck for performance when considering the whole application.…”

Section: B Performance and Energy Efficiencymentioning

confidence: 99%

A 142MOPS/mW integrated programmable array accelerator for smart visual processing

Das

Rossi

Martin

et al. 2017

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

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Due to increasing demand of low power computing, and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energyefficient programmable accelerators. This paper proposes an Integrated Programmable-Array accelerator (IPA) architecture based on an innovative execution model, targeted to accelerate both data and control-flow parts of deeply embedded vision applications typical of edge-nodes of the Internet of Things (IoT). In this paper we demonstrate the performance and energy efficiency of IPA implementing a smart visual trigger application. Experimental results show that the proposed accelerator delivers 507 MOPS and 142 MOPS/mW on the target application, surpassing a low-power processor optimized for DSP applications by 6x in performance and by 10x in energy efficiency. Moreover, it surpasses performance of state of the art CGRAs only capable of implementing data-flow portion of applications by 1.6x, demonstrating the effectiveness of the proposed architecture and computational model.

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Section: B Performance and Energy Efficiencymentioning

confidence: 99%

A 142MOPS/mW integrated programmable array accelerator for smart visual processing

Das

Rossi

Martin

et al. 2017

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The MORPHEUS approach has been evaluated by the production of a prototype chip [41]. Figure 12 shows a picture of this chip.…”

Section: Chip Prototypementioning

confidence: 99%

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

Grasset¹,

Millet²,

Bonnot³

et al. 2010

Int J Parallel Prog

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Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on This work was supported in part by the European Union in the 6th R&D Framework Program (MORPHEUS IST project, number 027342).A. Grasset (B) · P. Millet · P. Bonnot · S. Yehia 329 the type of application and their data flow. Existing solutions either offer fine grain FPGAs, which rely on a hardware synthesis flow and offer the maximum degree of flexibility, or coarser grain solutions, which are usually more suitable for a particular type of data flow and applications. In this paper, we present the MORPHEUS architecture, a versatile reconfigurable heterogeneous System-on-Chip targeting streaming applications. The presented architecture exploits different reconfigurable technologies at several computation granularities that efficiently address the different applications needs. In order to efficiently exploit the presented architecture, we implemented a complete software solution to map C applications to the reconfigurable architecture. In this paper, we describe the complete toolset and provide concrete use cases of the architecture.

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“…The MORPHEUS chip was designed and fabricated using a CMOS 90nm process of ST Microelectronics [Rossi et al 2009]. A limited area budget forced size limits on the individual cores.…”

Section: The Chip Prototypementioning

confidence: 99%

Morpheus

Voros

Hübner²,

Becker³

et al. 2013

ACM Trans. Embed. Comput. Syst.

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Recently, system designers are facing the challenge of developing systems that have diverse features, are more complex and more powerful, with less power consumption and reduced time to market. These contradictory constraints have forced technology providers to pursue design solutions that will allow design teams to meet the above design targets. In that respect, this paper introduces an innovative technology platform, called MORPHEUS, which intents to provide complete design framework for dealing with the aforementioned challenges. MORPHEUS consists of a state of the art architecture that encompasses heterogeneous reconfigurable accelerators for implementing on the same hardware architecture applications with varying characteristics and a tool chain that, through a software oriented approach, eases the implementation of highly complex applications with heterogeneous characteristics. The proposed approach has been tested and evaluated through state of the art cases studies borrowed from complementary application domains.

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A heterogeneous digital signal processor implementation for dynamically reconfigurable computing

Cited by 8 publications

References 7 publications

A 142MOPS/mW integrated programmable array accelerator for smart visual processing

A 142MOPS/mW integrated programmable array accelerator for smart visual processing

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

Morpheus

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