A high abstraction, high accuracy power estimation model for networks-on-chip

Abstract

Due to the vast number of alternatives in the design space of NoCbased MPSoCs, fast and accurate performance evaluation approaches can result in earlier -and often better -design decisions. Important design metrics for mobile embedded systems include power dissipation and energy consumption. To speed-up the evaluation of such metrics, state-of-the-art research proposes abstract models of the NoC interconnect, employing, for example, TLM SystemC, analytical descriptions and graph descriptions. Power parameters used at higher abstraction models (e.g. TLM) frequently rely upon data generated at lower abstraction levels (e.g. RTL). This paper presents an abstract model of a NoC coupled with a power estimation model, aiming to provide accurate estimations early on the design flow. Despite being abstract, this model considers typical NoC communication behavior such as congestion and burst transmissions, leading to accurate results compared to industrial tools. A proof-of-concept implementation using the Ptolemy II framework demonstrates the strength of this approach, showing that it is possible to use abstract models to estimate power and energy without incurring excessive accuracy loss. Other benefits of abstract modeling are increased system observability and simplicity of design space exploration. System observability is demonstrated with a graphic tool enabling the visualization of the power dissipation at runtime.

Model-based design flow for NoC-based MPSoCs

“…It uses an actor-oriented simulation framework that captures the dynamic behavior of the NoC components and feeds its parameters to a group of Scopes, providing accurate performance evaluation. The accurate performance evaluation is achieved by calibrating the proposed high level models using a reference design model, for instance an RTL implementation, as shown in [5].…”

“…The proposed approach employs a set of mapping heuristics, while the mapping process is merely manual in the reviewed works. In addition, the proposed approach allows accurate power analysis by using the rate-based power NoC model (in practice, an error of 0% when compared to the RTL simulation and 5% when compared to a commercial tool) [5]. This feature is another contribution of this work due to the fact that the rate-based power model considers low-level effects (congestion and burtiness) that are essential to verity the occurrence of hotspots.…”

Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip

“…Networks-on-chip are considered in [20]. The work presented in [20] indicates that power estimation considering only the total volume of data transported incurs inaccuracies since it abstracts away congestion.…”

“…Networks-on-chip are considered in [20]. The work presented in [20] indicates that power estimation considering only the total volume of data transported incurs inaccuracies since it abstracts away congestion. The proposed rate-based methodology measures traffic in a given sample period similarly as the approach follow in [20].…”

“…The work presented in [20] indicates that power estimation considering only the total volume of data transported incurs inaccuracies since it abstracts away congestion. The proposed rate-based methodology measures traffic in a given sample period similarly as the approach follow in [20]. The rate-based methodology is used in [20] with linear regression to develop power models for the Hermes NoC where it is shown to decrease the error to around 6% compared with Synopsys PrimePower.…”