A high density floating-gate EEPROM cell

Yeargain, J.R.; Kuo, C.

doi:10.1109/iedm.1981.189989

Cited by 14 publications

(4 citation statements)

References 3 publications

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“…NOR flash memory is mainly used for code storage because of its fast random access time. MLC NOR flash memory mainly uses channel hot electrons (CHE) for programming [4,5] . With sufficient drain bias, the minority carriers cause impact ionization at the drain side; the carriers which gain enough energy from the lateral field overcome the barrier and are injected into the floating gate.…”

Section: Introductionmentioning

confidence: 99%

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

Shi

Hong

Hu³

et al. 2009

J. Semicond.

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This paper presents an implementation for improving muti-level cell NOR flash memory program throughput based on the channel hot electron (CHE) temperature characteristic. The CHE Ig temperature characteristic is analyzed theoretically with the Lucky electron model, and a temperature self-adaptive programming algorithm is proposed to increase Ig according to the on-die temperature. Experimental results show that the program throughput increases significantly from 1.1 MByte/s without temperature self-adaptive programming to 1.4 MByte/s with the proposed method at room temperature. This represents a 30% improvement and is 70 times faster than the program throughput in Ref. [1].

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Section: Introductionmentioning

confidence: 99%

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

Shi

Hong

Hu³

et al. 2009

J. Semicond.

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“…The leakage current attributed to BBT is the so-called 'gate-induced drain leakage current' (I gidl ) and is considered to be one of the major components of leakage current in MOS transistors in the off state [2,3]. It has been detected in dynamic random access memory cells (DRAM), electrically erasable programmable read only memory (EEPROM) and dynamic MOS logic circuits [4][5][6][7]. Thus, it is necessary to model and assess the main sources of this current in order to minimize it and to foresee better technological solutions.…”

Section: Introductionmentioning

confidence: 99%

The n-type metal oxide semiconductor field-effect transistor bias impact on the modelling of the gate-induced drain leakage current

Touhami¹,

Bouhdada²

2002

Semicond. Sci. Technol.

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The band-to-band tunnelling (BBT) effect in an n-type metal-oxide semiconductor field-effect transistor (n-MOSFET) is attributed not only to the transverse electric field E T but also to the lateral electric field E L in the gate-to-drain overlap region. The main sources of these electric fields are the gate-source (V gs ) and drain-source (V ds ) voltages. The modelling of the gate-induced drain leakage current, I gidl , associated with BBT remains always dependent on the drain-gate voltage, V dg , whatever the applied values of V gs and V ds , which cannot describe accurately the evolution of the I gidl current according to biases. Therefore, it is necessary to clarify the impact of V gs and V ds separately. In this paper, we propose a new model of the I gidl current, which can describe the BBT effect in n-MOSFETs under various V gs and V ds biases.

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“…3 It has been detected in dynamic random access memory cells, electrically erasable programmable read-only memory, and dynamic metal-oxide-semiconductor logic circuits. [4][5][6] In this work we propose a new method to calculate the I gidl current, which takes into account the spatial distribution of the transverse electric field and the doping profile in the drain in the gate-drain overlap region. A Gaussian distribution can be used to model the density of donor or acceptor type of defects in the oxide located above the gate-drain overlap region.…”

Section: Introductionmentioning

confidence: 99%

Modeling of gate-induced drain leakage current in n-type metal–oxide–semiconductor field effect transistor

Touhami

Bouhdada

2001

Journal of Applied Physics

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A high density floating-gate EEPROM cell

Cited by 14 publications

References 3 publications

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

The n-type metal oxide semiconductor field-effect transistor bias impact on the modelling of the gate-induced drain leakage current

Modeling of gate-induced drain leakage current in n-type metal–oxide–semiconductor field effect transistor

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