A high frequency fully differential BiCMOS operational amplifier

Abstract

This paper presents a BiCMOS differential operational amplifier designed for use in switched-capacitor circuits. This BiCMOS op-amp offers an infinite input resistance, a d-c gain of 100dB, a unity-gain frequency of 90MHz with 45" phase margin and a slew rate of 150V/ps. The op-amp is unity gain stable with 7 pF of capacitive loading. The circuit is operated from a f 5 V power supply and dissipates 125mW. The op-amp is integrated in the 3.0 GHz, 2pm MIT BiCMOS process with an active die area of 1.0"x 1. 2". IntroductionThe increasing interest in high performance integrated analog and digital mixed processing systems drives the need for high performance switched capacitor analog circuits such as switched capacitor filters [4] and analog-to-digital converters.[7] Such analog circuits often require high performance operational amplifiers with a high frequency capability and high d-c gain.[8] The key advantage of implementing mixed signal systems in BiCMOS process technology is that for analog circuits, bipolar devices offer a transconductance that is generally higher compared to MOS devices leading to, for a given area, higher speed and higher gain. The CMOS devices offer high density logic in addition to capability for switched capacitor analog circuit architectures. A fully differential pipeline A/D architecture is desirable for implementation in a mixed signal environment. This paper describes a fully differential BiCMOS operational amplifier that is designed for use in switched capacitor analog circuits. The MIT BiCMOS ProcessThe focus of the MIT BiCMOS process is on building high precision and high speed analog/digital mixed systems for 1OV operation.[l] The process design reflects an emphasis on high performance analog circuit capability. The MIT BiCMOS process development approach is to integrate the bipolar devices into an existing twin well CMOS process. The vertical n-p-n devices are fabricated in a selective epitaxial layer deposited after the LOCOS field oxidation step of the CMOS process.[2] This epitaxial layer is deposited on n+ buried islands, located in p-wells. The non-optimized vertical p-n-p bipolar structures are formed by depositing the selective epitaxial layer on CMOS p-wells, without n+ buried islands, thus using the wells as the collectors. Since there is no buried layer for the p-n-p, its collector resistance is much higher than its n-p-n counterpart. It should be noted that the p-n-p transistors are junction isolated. The interconnect system for this BiCMOS process uses a single level of metal and polysilicon. Op-Amp Circuit DescriptionThe BiCMOS op-amp performance objectives are derived from the requirements of high performance switched capacitor analog circuits. The key design goals are a high unity gain frequency, high d-c gain and an infinite input resistance. The op-amp is a fully differential, two-stage design. The fully differential architecture enables good high frequency power supply rejection ratio in addition to increased dynamic range. Fig. 1 shows the basic op-amp circuit wit...

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