A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators

Abstract

GPUs became the reference platform for both training and inference phases of Convolutional Neural Networks (CNN) due to their tailored architecture to the CNN operators. However, GPUs are power-hungry architectures. A path to enable the deployment of CNNs in energy-constrained devices is adopting hardware accelerators for the inference phase. The design space exploration of CNNs using standard approaches, such as RTL, is limited due to their complexity. Thus, designers need frameworks enabling design space exploration that delivers accurate hardware estimation metrics to deploy CNNs. This work proposes a framework to explore CNNs design space, providing power, performance, and area (PPA) estimations. The heart of the framework is a system simulator. The system simulator front-end is TensorFlow, and the back-end is performance estimations obtained from the physical synthesis of hardware accelerators, not only from components like multipliers and adders. The first set of results evaluate the CNN accuracy using integer quantization, the accelerators PPA after physical synthesis, and the benefits of using a system simulator. These results allow a rich design space exploration, enabling selecting the best set of CNN parameters to meet the design constraints.

Guest Editorial: Special Issue Based on the 12th Edition of the Latin American Symposium on Circuits and Systems

“…In [4], Juracy et al reported that a path to enable the deployment of CNNs in energy-constrained devices is adopting hardware accelerators for the inference phase. The authors propose a framework to explore CNNs design space, providing Digital Object Identifier 10.1109/TCSI.2021.3115924 power, performance, and area (PPA) estimations using the system simulator front-end, TensorFlow.…”