A High Level Power Model for the Nostrum NoC

Penolazzi, Sandro; Jantsch, Axel

doi:10.1109/dsd.2006.9

Cited by 33 publications

(13 citation statements)

References 3 publications

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“…We have also varied k the diameter of the Hk+1. For the power model, we used the parameters for 1GHZ frequency and 0.18-micron CMOS as described in [39], [40], and [41]. Fig.9 shows that dynamic power dissipated by all three algorithms is very close to each other's.…”

Section: Simulation Resultsmentioning

confidence: 99%

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All-To-All Broadcast in Hexagonal Torus Networks On-Chip

Touzene

2015

IEEE Trans. Parallel Distrib. Syst.

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Hexagonal torus networks are special family of Eisenstein-Jacobi (EJ) Networks which have gained popularity as good candidates network On-Chip (NoC) for interconnecting Multiprocessor System-on-Chips (MPSoCs). They showed better topological properties compared to the 2D torus networks with the same number of nodes. All-to-all broadcast is a collective communication algorithm used frequently in some parallel applications. Recently, an off-chip all-to-all broadcast algorithm has been proposed for hexagonal torus networks assuming half-duplex links and all-ports communication. The proposed all-to-all broadcast algorithm does not achieve the minimum transmission time and requires 24k extra buffers, where k is the network diameter. We first extend this work by proposing an efficient all-to-all broadcast on hexagonal torus networks under full-duplex links and all-ports communications assumptions which achieves the minimum transmission delay but requires 36k extra buffers per router. In a second stage, we develop a new all-to-all broadcast more suitable for hexagonal torus network on-chip that achieves optimal transmission delay time without requiring any extra buffers per router. By reducing the amount of buffer space, the new all-to-all broadcast reduces the routers cost which is an important issue in NoCs architectures.

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Section: Simulation Resultsmentioning

confidence: 99%

“…We selected NS2 simulator for its flexibility and because most of the known NOC simulators allow only specific network topologies such as ring, mesh, etc. We plugged in our NS2 simulation model the power model described in Nostrum NOC [39] [40]. We considered only the dynamic power consumption in the buffers and in the wires.…”

Section: Simulation Resultsmentioning

confidence: 99%

All-To-All Broadcast in Hexagonal Torus Networks On-Chip

Touzene

2015

IEEE Trans. Parallel Distrib. Syst.

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“…One of the most important challenges in designing such MPSoCs is the fast and correct power estimation. There are several techniques to estimate the power consumption on microprocessors, but there are few techniques to estimate the power consumption in NoCs [1].…”

Section: Introductionmentioning

confidence: 99%

NoC Power Estimation at the RTL Abstraction Level

Guindani

Reinbrecht

Raupp

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

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The increasing use of mobile electronic devices forces the design of integrated circuits to consider low power techniques. Current power estimation models for oCs capitalize mostly in the volume of information transmitted through the network. This work presents a more precise oC power estimation model, based in buffer reception rates, according to the traffic scenario applied to the network. Results show the accuracy of the model compared to industrial power estimation tools, with reduced execution time. The proposed method allows exploring the oC design space, being employed to evaluate the benefit on using the multicast service.

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“…They proposed different modeling methodologies for node switches, internal buffers and interconnection wires inside switch fabric architectures. A power model for the Nostrum NoC has been proposed in [15]. For this purpose an empirical power model of links and switches has been formulated and validated with the synopsys power compiler.…”

Section: Introductionmentioning

confidence: 99%

New approach to calculate energy on NoC

Ghadiry

Nadi

Rahmati

2008

2008 International Conference on Computer and Communication Engineering

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Low scalability and power efficiency of the shared bus in SoCs is a motivation to use on chip networks instead of traditional buses. In this paper we have modified the Orion power model to reach an analytical model to estimate the average message energy in KAry n-Cubes with focus on the number of virtual channels. Afterward by using the power model and also the performance model proposed in [11] the effect of number of virtual channels on Energy-Delay product have been analyzed. In addition a cycle accurate power and performance simulator have been implemented in VHDL to verify the results.

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A High Level Power Model for the Nostrum NoC

Cited by 33 publications

References 3 publications

All-To-All Broadcast in Hexagonal Torus Networks On-Chip

All-To-All Broadcast in Hexagonal Torus Networks On-Chip

NoC Power Estimation at the RTL Abstraction Level

New approach to calculate energy on NoC

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