A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond

Hayashi, F.; Kitakata, M.

doi:10.1109/vlsit.1992.200634

Cited by 11 publications

(2 citation statements)

References 3 publications

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“…The transfer characteristics of the SC-SWDTG TFTs with a top silicon nitride liner of 100 nm, with/without the RTA treatment are shown in figure 3. To further include and enhance the strain effect into the poly-Si channels [15,16,[19][20][21], improve the crystallinity of the poly-Si channels [26], and decrease the total trap density (N T ) in the poly-Si channels [26,27], a high-temperature and transient treatment was implemented by the RTA process at 1050 °C for 1 s. Nevertheless, the mean grain size is only mildly affected by the RTA treatment because the variation of the mean grain size is slight before and after an additional RTA treatment [28]. Thus, the SC-SWDTG TFT-B shows a higher drain current than that of the SC-SWDTG TFT-A.…”

Section: Impacts Of Rapid Thermal Annealingmentioning

confidence: 99%

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High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique

Hsieh

Kuo

Lin

et al. 2017

Semicond. Sci. Technol.

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In this paper, strained channel-sidewall damascened tri-gate polycrystalline silicon thin-film transistors (SC-SWDTG TFTs) have been successfully fabricated and then demonstrated by an innovative process flow. This process flow without the use of advanced lithography processes combines the sidewall damascened technique (SWDT) and two strain techniques, namely, the strain proximity free technique (SPFT), and the stress memorization technique (SMT), in the poly-Si channels. It has some advantages: (1) the channel shapes and dimensions can be effectively controlled by the wet etching processes and the deposition thickness of the tetraethoxysilane (TEOS) oxide; (2) the source/drain (S/D) resistance can be significantly decreased by the formation of the raised S/D structures; (3) the SPFT, SMT, and the rapid thermal annealing (RTA) treatment can enhance the performance of the SC-SWDTG TFTs without the limitation of the highly scaling stress liner thickness in deep-submicron TFTs. Thus, the SC-SWDTG TFTs exhibit a steep subthreshold swing (S.S.)∼110 mV/dec., an extremely small drain induced barrier lowing (DIBL) ∼12.2 mV V −1 , and a high on/off ratio ∼10 7 (V D =1 V) without plasma treatments for future three-dimensional integrated circuits (3D ICs) applications.

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Section: Impacts Of Rapid Thermal Annealingmentioning

confidence: 99%

“…The SC-SWDTG TFTs with the RTA treatment show a steeper A.S.S. and a lower DIBL due to the improved crystallinity of the poly-Si channels and the less N T in the poly-Si channels [25,26]. The N T can be expressed by the following formula (1).…”

Section: Impacts Of Rapid Thermal Annealingmentioning

confidence: 99%