A high-performance reconfigurable 2-D transform architecture for H.264

Abstract

The 4x4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4x4 forward and inverse transforms for H.264 are proposed. A high-performance reconfigurable 2-D architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18um CMOS technology. The proposed design is more efficient than the existing typical designs. Under a clock frequency of 100 Mhz, the architecture allows the realtime processing of 4096x2048 at 60fps. I. PE