No abstract

The 4x4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4x4 forward and inverse transforms for H.264 are proposed. A new dynamic reconfigurable architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18um CMOS technology. Under a clock frequency of 200 Mhz, the architecture allows the real-time processing of 4096x2048 at 30fps with the area cost of 5140 gates and the power dissipation of 15.64 mW.I.

Two dimensional discrete wavelet transform (2D-DWT) has been adopted as a coding tool of JPEG 2000 image coding and MPEG-4 still texture coding. To make it suitable for real-time image processing applications, it is essential to develop custom VLSI chips for computation of 2D-DWT. A new high efficient architecture is proposed for 2D 1-level DWT, with the feature of original data is scanned by group and no temporal buffer is needed. Comparison results show our proposed architecture can provide a higher speed at less hardware consume.I.

No abstract

The 4x4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4x4 forward and inverse transforms for H.264 are proposed. A high-performance reconfigurable 2-D architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18um CMOS technology. The proposed design is more efficient than the existing typical designs. Under a clock frequency of 100 Mhz, the architecture allows the realtime processing of 4096x2048 at 60fps. I. PE