A high-performance reconfigurable VLSI architecture for vbsme in H.264

A low power and standard-compliant RDO motion estimation hardware architecture for VBSME

“…A comparison between the proposed circuit and previous typical VBSME circuits for H.264 is presented in Table II. Among the architectures, the proposed one can provide the lowest redundant load ration (when SearchRange= 16) than that of reference [7], [10], [11], [12], [13], which means every pixel in the search window is loaded only once in the search process of certain current MB. Furthermore, except [13], all reference are based on SAD only criteria which would results in significant RD drop compared to original H.264 standard.…”

“…[10], [11], [12] proposed a 2-D systolic array architecture with 256 PEs for FSVBSME. All these architectures are actually implementing the zero biased FSVBSME, which can cause a RD drop compared to the ME algorithms in the H.264 JM reference software.…”

An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC

“…The IME processor architecture in [19] is based on a 2-D systolic processor array and minimizes the off-chip memory bandwidth using local memories to achieve the highest level of on-chip data reuse. In order to also obtain high data reuse, the architecture presented in [20] makes a three scan direction search through a reconfigurable 2D computing array and 16 local SRAMs. The design proposed in [21] uses a simplified prediction motion vector combined with an early termination motion estimation to reduce the computation complexity of the IME.…”

“…Indeed, many VLSI implementations propose 2D systolic arrays to be more suitable for high-end real-time usage. References which adopt the complete FSBMA include the 2D architecture with a simple regular control in [16], the novel memory-access with minimum off-chip memory bandwidth in [19], the highperformance reconfigurable architecture to support a scan format for a high data reuse within the search area in [20], the bit serial architecture in [22] and the high throughput design in [39]. Modifications of the FSBMA to reduce either hardware or computing time, at the cost of introducing some video quality loss, can be found in the soft algorithm to simplify the predicted MV and the early termination of motion search used in [21], the multi-resolution IME algorithm presented in [23], the adaptive size in the search area depending on the degree of motion activity in [24,25], the modified algorithm to reduce hardware based on data dependency of motion vector prediction, pixel truncation and subsample proposed in [18], the IP with coarse and fine searches in [26] and the inter-candidate 4-parallel data reuse scheme with 16 2D PE-arrays in [27].…”

Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

“…Many hardware architectures for ME algorithms using 8 bits/ pixel video frames are proposed in the literature and several examples can be found in [8]- [12]. In [8], a hardware architecture for hierarchical ME with 8 bits/pixel representation and an example FPGA implementation together with a hardware complexity analysis is provided.…”