A high-speed AES design resistant to fault injection attacks

Mestiri, Hassen; Kahri, Fatma; Bouallègue, Belgacem; Machhout, Mohsen

doi:10.1016/j.micpro.2015.12.002

Cited by 32 publications

(34 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For each given number of protected bits we performed a set of fault injection experiments in which only the previously identified errors have been considered. [8] 85.96% 14.45% N.A. 49.02% Chu [9] 100.00% 81.99% N.A.…”

Section: Error Detection Capability Analysismentioning

confidence: 99%

“…The main issue in these solutions is the area or working frequency overhead. More recent proposals have been presented in [8], [9]. In [8], the computation of each AES round is duplicated and results are compared.…”

Section: Introduction and Related Workmentioning

confidence: 99%

“…More recent proposals have been presented in [8], [9]. In [8], the computation of each AES round is duplicated and results are compared. In [9], the AES original input is encoded into two different polynomial residue number system (which is not the residue checking referred in the current paper).…”

Section: Introduction and Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis

Lasheras

Canal

Rodríguez

et al. 2020

2020 IEEE 26th International Symposium on on-Line Testing and Robust System Design (IOLTS)

View full text Add to dashboard Cite

Hardware acceleration circuits for cryptographic algorithms are largely deployed in a wide range of products. The HW implementations of such algorithms often suffer from a number of vulnerabilities that expose systems to several attacks, e.g., differential fault analysis (DFA). The challenge for designers is to protect cryptographic accelerators in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting hardware accelerators implementing AES and SHA-2 (which are two widely used NIST standards) against DFA. The proposed technique exploits partial redundancy to first detect the occurrence of a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the overhead introduced is 8.32% for AES and 3.88% for SHA-2 in terms of area, 0.81% for AES and 12.31% for SHA-2 in terms of power with no working frequency reduction. Moreover, a comparative analysis showed that our proposal outperforms the most recent related countermeasures.

show abstract

Section: Error Detection Capability Analysismentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis

Lasheras

Canal

Rodríguez

et al. 2020

2020 IEEE 26th International Symposium on on-Line Testing and Robust System Design (IOLTS)

View full text Add to dashboard Cite

show abstract

“…A solution to the fault based injection attacks has been provided in [24]. The proposed scheme is independent of S-box and inverse S-box and achieves more than 95% fault coverage.…”

Section: Related Workmentioning

confidence: 99%

RK-AES: An Improved Version of AES Using a New Key Generation Process with Random Keys

Saha

Geetha

Kumar

et al. 2018

Security and Communication Networks

View full text Add to dashboard Cite

Advanced Encryption Standard (AES) is a standard algorithm for block ciphers for providing security services. A number of variations of this algorithm are available in network security domain. In spite of the strong security features, this algorithm has been recently broken down by the cryptanalysis processes. Therefore, it is required to improve the security strength of this algorithm as AES is popular in commercial use. In this paper, we have shown the reasons of the loopholes in AES and also have provided a solution by using our Symmetric Random Function Generator (SRFG). The use of randomness in the key generation process in block cipher is novel in this domain. We have also compared our results with the original AES based upon some parameters such as nonlinearity, resiliency, balancedness, propagation characteristics, and immunity. The results show that our proposed version of AES is better in withstanding attacks.

show abstract

“…Also we can inject faults temporarily in the cryptographic system in reason to retrieve the secret key or state. Many error detection schemes have been implemented to make a robust hardware design and to secure cryptographic systems against faults injection attacks [12][13][14][15][16][17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Fault Attacks Resistant Architecture for KECCAK Hash Function

Kahri¹,

Mestiri²,

Bouallègue³

et al. 2017

ijacsa

Self Cite

View full text Add to dashboard Cite

Abstract-The KECCAK cryptographic algorithms widely used in embedded circuits to ensure a high level of security to any systems which require hashing as the integrity checking and random number generation. One of the most efficient cryptanalysis techniques against KECCAK implementation is the fault injection attacks. Until now, only a few fault detection schemes for KECCAK have been presented. In this paper, in order to provide a high level of security against fault attacks, an efficient error detection scheme based on scrambling technique has been proposed. To evaluate the robust of the proposed detection scheme against faults attacks, we perform fault injection simulations and we show that the fault coverage is about 99,996%. We have described the proposed detection scheme and through the Field-Programmable Gate Array analysis, results show that the proposed scheme can be easily implemented with low complexity and can efficiently protect KECCAK against fault attacks. Moreover, the FieldProgrammable Gate Array implementation results show that the proposed KECCAK fault detection scheme realises a compromise between implementation cost and KECCAK robustness against fault attacks.

show abstract

A high-speed AES design resistant to fault injection attacks

Cited by 32 publications

References 5 publications

Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis

Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis

RK-AES: An Improved Version of AES Using a New Key Generation Process with Random Keys

Fault Attacks Resistant Architecture for KECCAK Hash Function

Contact Info

Product

Resources

About