2017
DOI: 10.1109/tcsi.2016.2633430
|View full text |Cite
|
Sign up to set email alerts
|

A High-Speed and Ultra Low-Power Subthreshold Signal Level Shifter

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

0
26
0

Year Published

2019
2019
2022
2022

Publication Types

Select...
7
2

Relationship

0
9

Authors

Journals

citations
Cited by 59 publications
(26 citation statements)
references
References 11 publications
0
26
0
Order By: Relevance
“…The power dissipation and propagation delay of advanced DCVS based level shifter obtained during the preliminary analysis is 99.9 pW and 250 pS, respectively. The generalized circuit diagram for current mirror based level shifter [6] design is given in figure 1.10. It consists of a basic current mirror composed of transistor Q1 and Q2.…”
Section: Level Shifter Circuitsmentioning
confidence: 99%
“…The power dissipation and propagation delay of advanced DCVS based level shifter obtained during the preliminary analysis is 99.9 pW and 250 pS, respectively. The generalized circuit diagram for current mirror based level shifter [6] design is given in figure 1.10. It consists of a basic current mirror composed of transistor Q1 and Q2.…”
Section: Level Shifter Circuitsmentioning
confidence: 99%
“…Ref. [16] proposed using a level-shifting capacitor to increase the conversion range, achieving a delay of 29ns with a power consumption of 61.5nW when the supply voltages, VDDL and VDDH, are 0.4V and 1.8V, respectively. Ref.…”
Section: Introductionmentioning
confidence: 99%
“…Several LSs have been proposed to get over the restrictions of traditional architectures. The LSs proposed in [12,13,14,15,16,17,18,19,20,21,22,23] employ CM-based structures. To minimize leakage power in standby mode, [12] cuts off the static current by a feedback PMOS.…”
Section: Introductionmentioning
confidence: 99%