A Sub-100mV Ultra-Low Voltage Level-Shifter Using Current Limiting Cross-Coupled Technique for Wide-Range Conversion to I/O Voltage

Abstract

In this paper, a sub-100mV ultra-low-voltage level-shifter for wide-range voltage conversion to I/O voltage is presented. The level-shifter uses a current limiting diode-connected transistor with crosscoupled transistor structure to reduce the minimum input voltage down to 100mV while covering a wide output voltage range up to I/O supply voltage (3V). We propose an improved split-control output buffer to reduce the static current from VDDH to VSS. The level-shifter is implemented using X-FAB 180nm HV CMOS process. The post-layout simulations show that the proposed structure achieves an average propagation delay of 7.57µs with a power consumption of 3.43nW when the supply voltages VDDL, VDDH, and input frequency are 100mV, 3V, and 1kHz, respectively. The design occupies 182.46µm 2 silicon area with a static power consumption of 3nW when VDDL and VDDH are 100mV and 3V, respectively, which is suitable for low power applications. INDEX TERMS Differential cascode voltage switch, level-shifter, low power, sub-threshold voltage, wide voltage range

An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0V

“…We have adopted a device selection and sizing technique similar to Ref. [4]. First, the input devices NM2 and NM3 are implemented with low-threshold voltage (LVT) n-type transistors to increase the strength of the pull-down network.…”

“…Voltage scaling technique is widely used to reduce power consumption in system-on-chips (SoCs) [1]. The aggressive scaling down in supply voltage has demanded level shifters (LSs) with an ultra-low input voltage of ≤200mV while maintaining the output range for the IO devices of 1.8-3.0V [2]- [4]. Designing an ultra-low input voltage LS with a wide voltage range has been a great challenge in low-power applications.…”

“…Often, conventional cross-coupled or current-mirror based LS fails to function when operating with ultra-low input voltage (≤200mV) [5]- [7]. To address this challenge while improving the output voltage range, several state-of-the-art LS architectures have been reported [4], [8]- [28]. Recently, LS integrated with time-borrowing latch has been proposed [29], which allows sampling of the input signal after the rising edge of the clock signal, making the circuit more robust against timing variation.…”

An Ultra-Low-Voltage Energy-Efficient Dynamic Fully-Regenerative Latch-Based Level-Shifter Circuit with Tunnel-FET & FinFET Devices

“…Level-shifter (LS) circuit is indispensable as it provides a signal interface across voltage domains. Thus, designing an ultra-low input voltage high-speed LS with a wide voltage range has been a great interest in low-power applications [1]- [6].…”

“…There are two types of LS architectures, namely differential cascode voltage switch (DCVS) LS [4]- [6] and conventional current mirror (CM) based LS circuits [1], [2], [7]. The DCVS-based LS architecture is a fully dynamic circuit but it suffers the problem of current contention between the pull-up and pull-down networks, limiting the voltage conversion range [7], [8].…”