An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0V

Abstract

Level converting is increasingly difficult in ultra-low voltage circuits with the aggressive scaling down of the input voltage. In this paper, we proposed a wide output range level shifter (LS) with the ultra-low input voltage. The proposed LS is integrated with a positive flip-flop function with a three-phase time borrowing scheme at the sampling edge. The working principle eliminates the current contention problem in the conventional cross-coupled level shifters, which allows a much higher output range at ultra-low input. The time borrowing technique also allows a relaxed timing constraint, which increases the timing margin and improves robustness against variation in ultra-low voltage circuits. The proposed LS is implemented with 45nm CMOS technology. Simulation results show that the proposed structure achieves a propagation delay of 10.01ns, power consumption of 11.23µW, and a power-delay-product (PDP) of 112,412ns • nW when converting an input signal of 200mV to an output level of 3V.

Input Voltage-Level Driven Split-Input Inverter Level Shifter for Nanoscale Applications

“…LSs face a challenge when up-converting sub-threshold voltages, as it causes the pull-down network areas to be too large and complex in practice [10][11][12][13]. Current-mirror-based architectures [7,10,14] perform better when a wide range of up-conversion is required, as they face more contention among pull-up and pull-down networks, which results in increased speed and reduced energy consumption. However, they tend to consume more static power.…”

“…An improved Wilson current mirror that utilizes mixed-threshold voltage devices has also been reported to address issues with conventional current-mirror-based LSs. In order to achieve even greater energy efficiency, the output stage of an inverting buffer Current-mirror-based architectures [7,10,14] perform better when a wide range of up-conversion is required, as they face more contention among pull-up and pull-down networks, which results in increased speed and reduced energy consumption. However, they tend to consume more static power.…”

A Novel Word Line Driver Circuit for Compute-in-Memory Based on the Floating Gate Devices

“…Commonly used structures can be summarized into two types. One is where the level shifter circuit [8][9][10] cooperates with the switching metal-oxide-semiconductor (MOS) to realize high-voltage control and transmission [11]. Since the level shifter circuit cannot directly generate high voltage, charge pumps are needed to realize the generation of various high voltages.…”

An energy‐efficient level shifter based on a differential cascade voltage switch structure

“…Matsuzuka et al 11 use a pre-amplifier comprising a logic error correction circuit which can generating an operation current only when the logic levels of the input and output do not correspond. Literature [14][15][16][17][18][19] are presented on the basis of DCVS architecture. Lanuzza et al 14 combine the multi-threshold CMOS design technique along with novel topological strategies to achieve fast response and low energy consumption.…”

“…Kabirpour and Jalali 15 introduce a new regulated cross coupled pull‐up network in order to improve delay and the dynamic power consumption. The LS reported in Ma et al 19 is integrated with a positive flip‐flop function with a three‐phase time borrowing scheme at the sampling edge, which eliminates the current contention problem in the conventional cross‐coupled level shifters. Maeng et al 20 present n‐ and p‐type periodically refreshed capacitive floating LS, which can generate a floating signal without additional bias voltage, and all coupling capacitors can be simultaneously refreshed.…”