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Level converting is increasingly difficult in ultra-low voltage circuits with the aggressive scaling down of the input voltage. In this paper, we proposed a wide output range level shifter (LS) with the ultra-low input voltage. The proposed LS is integrated with a positive flip-flop function with a three-phase time borrowing scheme at the sampling edge. The working principle eliminates the current contention problem in the conventional cross-coupled level shifters, which allows a much higher output range at ultra-low input. The time borrowing technique also allows a relaxed timing constraint, which increases the timing margin and improves robustness against variation in ultra-low voltage circuits. The proposed LS is implemented with 45nm CMOS technology. Simulation results show that the proposed structure achieves a propagation delay of 10.01ns, power consumption of 11.23µW, and a power-delay-product (PDP) of 112,412ns • nW when converting an input signal of 200mV to an output level of 3V.

This paper analyses theoretically the effect of transportation and housing subsidies on urban sprawl, modal choice decisions and urban spatial structure using a spatial general equilibrium model in a monocentric city with two transport modes. Our analysis shows that public transit subsidy leads to urban shrink, whilst subsidizing automobile and housing make the city sprawl. We also find the effects of the other factors on urban sprawl, such as households income and demand, rural land rent, the income tax rate, the total fixed cost of public transit and automobile and the travelling marginal cost of public transit and automobile. Furthermore, this paper also studies how to maximize the urban-area-wide spatial equilibrium utility level.

Circuits based on tunneling FET (TFET) devices are fueling the beyond CMOS logic design, meeting the ultra-low-power demands for Internet-of-Things (IoT) applications. This paper presents a highly energy-efficient hybrid TFET/FinFET level shifter (LS) circuit, providing a robust signal up-conversion from deep subthreshold voltage. A pulse-triggered dynamic fully-regenerative latch and two modified dynamic current generators are incorporated to overcome the timing variation of input differential signals and current contention in the cross-coupled circuit. The simulation results show that the hybrid TFET/FinFET LS circuit has achieved a low propagation delay, dynamic power consumption, and power-delay-product (PDP) of ≤378 ps, ≤39.6 µW, and ≤13,950 ns • nW, respectively while converting the input signal from the ultra-low-voltage of sub-50mV to the nominal supply voltage of FinFET (0.8-1.2V). The proposed architecture has achieved up to 2.71-to-15.99× improvement in PDP compared to the reported state-of-the-art LS architectures.Index Terms-Level shifter (LS), tunnel field-effect transistor (TFET), subthreshold circuit, ultra-low power, hybrid design, time-borrowing

The increasing number of voltage domains along with the size of the data bus requires an exponential increase in the number level shifter (LS) circuits for signal interfacing, creating an exploding in silicon area and power consumption. Higher area-efficiency can be attained by further improving the integration density of the LS circuit. In this paper, we present a multi-function ultra-low-voltage LS with re-configurable logic with embedded time-borrowing latch. The proposed circuit is implemented on CMOS 45nm technology. It is capable of converting the input voltage of 0.3 V to an output voltage of 1.8 V with an input frequency of 1 MHz. The proposed architecture has achieved a superior area efficiency with reduced transistors number of 2.4× and reduced power delay product (PDP) of 4.65× compared with its discrete logic block level implementation when the input voltage, output voltage, and the input frequency are 0.3 V, 1.8 V, and 1 MHz, respectively. The average propagation delay and power consumption are 52.7 ns and 34.6 nW, respectively. INDEX TERMSLevel shifter, ultra-low-voltage, embedded re-configurable logic, time-borrowing latch technique.