A high speed low input current low voltage CMOS current comparator

Moolpho, K.; Ngarmnil, J.; Sitjongsataporn, Suchada

doi:10.1109/iscas.2003.1205593

Cited by 7 publications

(1 citation statement)

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“…Further, [31]- [34] employ various biasing techniques to reduce input impedance and hence achieve higher speeds of operation while maintaining lower power consumption. Specifically, simple biasing method is used in [31] and [33] whereas [32] uses negative feedback scheme at the transimpedance stage with an aim to achieve a very large loop-gain while maintaining the transformed voltage signal gain at the lowest swing in order to achieve speed…”

Section: Introductionmentioning

confidence: 99%

High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

Bhatia

Pandey

Bhattacharyya

2016

IJECE

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A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.

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