A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices

Abstract

Low density parity check (LDPC) decoding process is known as compute intensive. This kind of digital communication applications was recently implemented onto graphic processing unit (GPU) devices for LDPC code performance estimation and/or for real-time measurements. Overall previous studies about LDPC decoding on GPU were based on the implementation of the flooding-based decoding algorithm that provides massive computation parallelism. More efficient layered schedules were proposed in literature because decoder iteration can be split into sublayer iterations. These schedules seem to badly fit onto GPU devices due to restricted computation parallelism and complex memory access patterns. However, the layered schedules enable the decoding convergence to speed up by two. In this letter, we show that: 1) layered schedule can be efficiently implemented onto a GPU device; and 2) this approach-implemented onto a low-cost GPU device-provides higher throughputs with identical correction performances (BER) compared to previously published results.Index Terms-Graphic processing unit (GPU), layered-based algorithm, low density parity check (LDPC), throughput optimized.

A DSEL for high throughput and low latency software‐defined radio on multicore CPUs

“…To create a socket, four parameters are required: its datatype (given as a template parameter), its associated task, its name, and its size. Finally, a "codelet" function need to be set (lines [14][15][16][17][18][19][20][21][22][23][24][25][26]. This codelet will be called when the task will be triggered.…”

“…Many SDR elementary blocks have been optimized for Intel® and ARM® CPUs. High throughput results have been achieved on GPUs; 19‐23 latency results are is still too high however to meet real time constraints and to compete with CPU implementations 22,24‐33 . This is mainly due to data transfers between the host (CPUs) and the device (GPUs), and to the nature of GPU designs, which are not optimized for latency efficiency.…”

Multi-Gbps LDPC Decoder on GPU Devices

“…GPU-based high-throughput LDPC decoders have been widely studied in the past years [21][22][23][24][25][26]. In [21], a high-throughput decoder based on layered scheduling was proposed.…”

“…GPU-based high-throughput LDPC decoders have been widely studied in the past years [21][22][23][24][25][26]. In [21], a high-throughput decoder based on layered scheduling was proposed. Some GPU-based optimizations were presented in [22] to obtain a high throughput, which reached a 1.27 Gbps peak throughput on a single GPU.…”

High-Speed Decoders for Polar Codes

“…The irregular data access patterns featured in turbo and LDPC decoders make efficient use of Single-Instruction Multiple-Data (SIMD) extensions present on today's processors difficult. To overcome the difficulty of efficiently accessing memory while decoding one frame and still achieve a good throughput, software decoders resorting to inter-frame parallelism (decoding multiple independent frames at the same time) are often proposed [11]- [13]. Inter-frame parallelism comes at the cost of higher latency, as many frames have to be buffered before decoding can be started.…”