A high-throughput reconfigurable Viterbi decoder

Li, Rongchun; Dou, Yong; Zhou, Jie; Lei, Guoqing

doi:10.1109/wcsp.2011.6096781

Cited by 8 publications

(17 citation statements)

References 12 publications

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“…Critical length is taken care by pipeline operation. One disadvantage in our design is that it requires more LUT resources as compared to the proposed architecture in [8]. Configuration time: 3 cycles are required to read K,L and R values.…”

Section: Implementation Results and Comparisonmentioning

confidence: 99%

“…Table III shows the results reported from other similar work. In [8], the authors considered only the code rates of � and i. The trellis diagram for these cases are simple, only two branches connect to and from each state between two successive steps of trellis.…”

Section: Implementation Results and Comparisonmentioning

confidence: 99%

“…M.F.N Batcha et al [7] reported an implementation of a Viterbi decoder for GPS, EDGE and WiMAX systems. In [8], Rongchun Li et al presented a reconfigurable Viterbi decoder, which could support constraint lengths from 3-9, code rates �, i with a maximum throughput of 202 Mbps. Most of the existing implementations of Viterbi decoders are for code rates of R = �.…”

Section: Related Workmentioning

confidence: 99%

“…In literature [2]- [8], several reconfigurable Viterbi decoder architectures are presented, but the reconfiguration is limited to code rate of � to !, and constraint length from 3 to 9. In [12] the authors presented a scalable architecture for code rate � Viterbi decoder.…”

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confidence: 99%

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A reconfigurable viterbi decoder for SDR and mobile communications

Pradhan

Nandy

2014

2014 International Conference on High Performance Computing and Applications (ICHPCA)

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Data rate grows monotonously in every new gen eration of wireless communication system and so does the error rate while transmitting through wireless channels. Hence channel coding, error detection and correction play a major role in overall system performance. Unlike Blockcodes, Convolutional code (CC) offers high error resiliance capacity by increasing their constraint length, instead of increasing the code redundancy. Viterbi de coders have been widely used as the decoder for convolutional codes. In this paper we present a dynamically reconfigurable Viterbi Decoder (VD). The proposed Viterbi decoder supports code rates of 1/2, 1/3,2/3,3/4,5/6, constraint lengths from 3-9, and arbitrary block lengths. The proposed decoder is synthesized in ISE and implemented on Xilinx XCV330T device. A throughput of 197 Mbps is achieved at frequency 197 MHz, which shows the architecture to be superior in terms of reconfiguration and throughput to reconfigurable Viterbi decoders on FPGA platform published in literature.

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Section: Implementation Results and Comparisonmentioning

confidence: 99%

Section: Implementation Results and Comparisonmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

mentioning

confidence: 99%

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A reconfigurable viterbi decoder for SDR and mobile communications

Pradhan

Nandy

2014

2014 International Conference on High Performance Computing and Applications (ICHPCA)

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“…Here, our proposed VD is also designed for the LTE system. Several VD architectures [1]- [7] have been proposed. These architectures often require a survivor memory unit (SMU) to produce the wanted output.…”

Section: Introductionmentioning

confidence: 99%

A memoryless Viterbi decoder for LTE systems

Lin

et al. 2012

The 1st IEEE Global Conference on Consumer Electronics 2012

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This paper presents a novel memoryless Viterbi decoder (VD) with a 4-level soft decision for long term evolution (LTE) systems. Based on the proposed architecture, the survivor memory can be eliminated totally, which will significantly reduce 50% of the total power dissipation. Finally, the proposed design consumes approximately 23.4K gates using 0.18 µm CMOS technology, and its power consumption is approximately 7.5 mW at 80 MHz.

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Efficient parallel implementation of three‐point viterbi decoding algorithm on CPU, GPU, and FPGA

Dou

Zou

2013

Concurrency and Computation

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SUMMARYIn wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G communications. However, the throughput of Viterbi decoder is constrained by the convolutional characteristic. Recently, the three‐point VDA (TVDA) was proposed to solve this problem. In TVDA, the whole procedure can be divided into three phases, the forward, trace‐back, and decoding phases. In this paper, we analyze the parallelism of TVDA and propose parallel TVDA on the multi‐core CPU, graphics processing unit (GPU), and field programmable gate array (FPGA). We demonstrate approaches that fully exploit its performance potential on CPU, GPU, and FPGA computing platforms. For CPU platforms, we perform two optimization methods, single instruction multiple data and multithreading to gain over 145 × speedup over the naive CPU version on a quad‐core CPU platform. For GPU platforms, we propose the combination of cached memory optimization, coalesced global memory accesses, codeword packing scheme, and asynchronous data transition, achieving the throughput of 404.65 Mbps and 12 × speedup over initial GPU versions on an NVIDIA GeForce GTX580 card and 7 × speedup over Intel quad‐core CPU i5‐2300, under the same manufacturing year and both with fully optimized schemes. In addition, for FPGA platforms, we customize a radix‐4 pipelined architecture for the TVDA in a 45‐nm FPGA chip from Xilinx (XC6VLX760). Under 209.15‐MHz clock rate, it achieves a throughput of 418.30 Mbps. Finally, we also discuss the performance evaluation and efficiency comparison of different flexible architectures for real‐time Viterbi decoding in terms of the decoding throughput, power consumption, optimization schemes, programming costs, and price costs.Copyright © 2013 John Wiley & Sons, Ltd.

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A high-throughput reconfigurable Viterbi decoder

Cited by 8 publications

References 12 publications

A reconfigurable viterbi decoder for SDR and mobile communications

A reconfigurable viterbi decoder for SDR and mobile communications

A memoryless Viterbi decoder for LTE systems

Efficient parallel implementation of three‐point viterbi decoding algorithm on CPU, GPU, and FPGA

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