A highly manufacturable 0.18 μm generation logic technology

Ikeda, Shuji; Yoshida, Yoshitaka; Shoji, K.; Kuroda, Kenichi; Komori, Kazuhiro; Suzuki, N.; Okuyama, K.; Kamohara, S.; Ishitsuka, Norio; Miura, Haruo; Murakami, Eiichi; Yamanaka, T.

doi:10.1109/iedm.1999.824242

Cited by 5 publications

(2 citation statements)

References 2 publications

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“…versus characteristics presented in Fig. 4, shows that this single work-function technology is capable of delivering performance comparable to published 1.5-V low-leakage dual work-function technologies [7], [8]. It needs to emphasized that performance similar to dual work-function technology is achieved in spite of using higher thermal budgets associated with DRAM integration, no source/drain junction salicidation, and more importantly, using single work-function gates.…”

Section: Resultsmentioning

confidence: 73%

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

Rengarajan

He²,

Ransom³

et al. 2002

IEEE Electron Device Lett.

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This letter reports on 1.5-V single work-function W/WN/n + -poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At of 1.5-V and 25 C, drive currents of 634 A/ m for 90-nm gate NMOS and 208 A-m for 110-nm gate buried-channel PMOS are achieved at 25 pA/ m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.

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Section: Resultsmentioning

confidence: 73%

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

Rengarajan

He²,

Ransom³

et al. 2002

IEEE Electron Device Lett.

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“…9. We use RT-polysilicon as a gate electrode since this film has fine and uniform grain, which is essential in order to suppress threshold voltage variation, especially in small size MOSFETs [12], [13]. RT-nitride spacers with a much shorter deposition time gives shallower junction extensions and improves rolloff, resulting in better uniformity of threshold voltage, as shown in Fig.…”

Section: Device Characteristicsmentioning

confidence: 99%

Process integration of single-wafer technology in a 300-mm fab, realizing drastic cycle time reduction with high yield and excellent reliability

Ikeda

Nemoto

Funabashi

et al. 2003

IEEE Trans. Semicond. Manufact.

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Abstract-In this paper, we discuss a new technology implemented with all, single-wafer processing for a 300-mm fab. Newly developed equipment and chemicals reduce the process time and provide cost savings. The combination of fully automated systems and single-wafer processing significantly reduces queuing time. The process has been re-integrated to eliminate long time processes and make it suitable for single-wafer technologies. As a result, a very aggressive cycle time (0.25 days/layer) with high yield, in double-polysilicon, sextuple-metal, 0.18-m LOGIC process has been demonstrated. High-performance devices with excellent reliability are also obtained. A new methodology for detecting parametric errors effectively in the early stages of production is implemented for quick yield ramp up.

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Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

Lee

Park

Kim

et al. 2003

Microelectronics Reliability

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A highly manufacturable 0.18 μm generation logic technology

Cited by 5 publications

References 2 publications

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

Process integration of single-wafer technology in a 300-mm fab, realizing drastic cycle time reduction with high yield and excellent reliability

Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

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