A highly reliable self-planarizing low-k intermetal dielectric for sub-quarter micron interconnects

Matsuura, M.; Tottori, I.; Goto, Kazuya; Maekawa, Kazuyoshi; Mashiko, Y.; Hirayama, Masaki

doi:10.1109/iedm.1997.650499

Cited by 10 publications

(11 citation statements)

References 6 publications

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“…Planarity is needed in multilevel interconnect technology because smooth surfaces are required to ensure good metal step coverage, 1 and to provide a flat enough field, within lithographic depth of focus capabilities, such that contact vias and metal wires can be patterned. 2,3 Failure to provide planar surfaces in the dielectric can result in electrical defects, electromigration problems, impairment of device reliability, and yield reduction.Reflow of dielectric films has been effective to a degree in reducing local variations in topography of multilevel interconnections. Phosphorus-doped silicon dioxide, or phosphosilicate glass (PSG), and phosphorus-and boron-doped silicon dioxide, or borophosphosilicate glass (BPSG), reflow processes have been commonly used to obtain insulating films with reasonably flat surfaces.…”

mentioning

confidence: 99%

Planarization Processes and Applications: I. Undoped GeO2 ‐ SiO2 Glasses

Simpson

Croswell

Reisman

et al. 1999

J. Electrochem. Soc.

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Ultralarge scale (ULSI) integrated circuits invariably require more than one level of interconnect metal. One of the main challenges in implementing such multilevel interconnect structures is planarization of the intermetal dielectric. Planarity is needed in multilevel interconnect technology because smooth surfaces are required to ensure good metal step coverage, 1 and to provide a flat enough field, within lithographic depth of focus capabilities, such that contact vias and metal wires can be patterned. 2,3 Failure to provide planar surfaces in the dielectric can result in electrical defects, electromigration problems, impairment of device reliability, and yield reduction.Reflow of dielectric films has been effective to a degree in reducing local variations in topography of multilevel interconnections. Phosphorus-doped silicon dioxide, or phosphosilicate glass (PSG), and phosphorus-and boron-doped silicon dioxide, or borophosphosilicate glass (BPSG), reflow processes have been commonly used to obtain insulating films with reasonably flat surfaces. 1,4,5 These films exhibit profiles over steps that get progressively smoother with higher phosphorus and boron concentration, reflecting the corresponding enhancement in viscous flow. However, decreasing thermal budgets and increasing via aspect ratios as well as the requirement of strict control of the dopant concentration have caused a transition to an alternative method for achieving planar surfaces, chemical mechanical polishing (CMP).CMP has been proven to achieve a measure of global planarization not previously possible with spin-on and resist etchback techniques. 6 However, CMP processes are hampered by pattern sensitivities, which cause regions on a chip to have thicker dielectric layers than other regions due to differences in the underlying topography. 7 Also, inconsistencies in reproducing polishing rates have also proven to be a problem. In fact, CMP is performed with empirical polishing rates and timed polishes. This results in a decrease in reliability and yield, and is costly.Conceptually, a glass that could be planarized within thermal budget constraints and still maintain good stress, electrical, and water solubility properties could eliminate the need for some, if not all, CMP steps, especially the CMP step for the first dielectric layer between the devices and the first-level metal, i.e., the poly-metal dielectric (PMD). Boron and/or phosphorus-doped SiO 2 films are unable to incorporate sufficient quantities of the dopant elements to reflow at a sufficiently low temperature before the glasses become unstable. In order to push the reflow temperature lower with the goal of planarizing reflow, an alternative chemical system, such as, GeO 2 -SiO 2 discussed below, is needed.There are several literature reports on the properties of the GeO 2 -SiO 2 system. [8][9][10]11 Only one of these 11 deals with GeO 2 glass films compositions greater than 25 mol %. The limited range of germanosilicate (GeO 2 ) compositions explored in most of these studies is not, ...

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mentioning

confidence: 99%

Planarization Processes and Applications: I. Undoped GeO2 ‐ SiO2 Glasses

Simpson

Croswell

Reisman

et al. 1999

J. Electrochem. Soc.

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“…Combinations of aluminum with various low-k dielectrics are under active investigation. [6][7][8] For the purpose of manufacturing, a metal-dielectric combination must satisfy many requirements with regard to strength and stability, compatibility with other processing steps, etc. 9 An important component of all these issues is the stability of the metal-dielectric interface.…”

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confidence: 99%

Metal/fluorinated-dielectric interactions in microelectronic interconnections: Rapid diffusion of fluorine through aluminum

Kim

Steinbrüchel

1999

Applied Physics Letters

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Rather surprising behavior has been observed when aluminum (Al) is in contact with fluorine-doped silicon dioxide (FSG). With Al deposited onto FSG, x-ray photoelectron spectroscopy shows that there is only a very minor reaction at the interface, producing a small amount of AlF3. No fluorine is observed in the bulk of the Al film, but fluorine diffuses readily through the Al even at room temperature and reacts at the free metal surface. On the other hand, with FSG deposited onto Al, the native aluminum oxide provides quite good protection against fluorine diffusion. By contrast, when pure Cu is in contact with FSG, there is almost no interaction or fluorine diffusion. Various approaches to reducing fluorine diffusion into a metal are also discussed, including using a diffusion barrier (TiN, Ta, TaN) or a suitable plasma treatment of the FSG before metal deposition.

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“…However, immersing the OSG film in boiling water for 30 min caused the Si-OH peak to appear in the FTIR spectra, whereas it remained stable for the FSG film even after immersion in boiling water for 2 h. Since OSG is more porous and less dense than FSG, moisture uptake in OSG should be easier due to its effective larger surface area, despite the presumption that adding CH 3 groups to the Si-O matrix could cause OSG to become hydrophobic. [1][2][3]6,[19][20][21] Such a susceptibility to moisture may adversely impact the electrical reliability of OSG in its integration with Cu metallization. Second, OSG is a hybrid material whose infrared spectrum comprises both organic and inorganic absorption peaks.…”

Section: Resultsmentioning

confidence: 99%

“…2 Low-k (k Ͻ 3.0) dielectrics are currently being extensively developed on both organic ͑carbon-based͒ and inorganic (SiO 2 -based͒ materials using both spin-on ͑SO͒ and chemical vapor deposition ͑CVD͒ techniques. [1][2][3][4][5][6][7][8][9][10] Although spin-on is the most widely used method, low-k films grown by CVD are recently receiving widespread attention for potential back-end-of-line applications. Remarkably, CVD techniques offer several key advantages, such as superior gap-filling capability and extremely uniform coating of large areas, which is crucial to future 300 mm wafers.…”

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confidence: 99%

Physical and Electrical Characteristics of F- and C-Doped Low Dielectric Constant Chemical Vapor Deposited Oxides

Shiung

Chiang

et al. 2001

J. Electrochem. Soc.

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This work compares the physical and electrical properties of two species of inorganic low dielectric constant ͑low-k͒ chemical vapor deposited ͑CVD͒ oxides, F-doped fluorinated silicate glass ͑FSG, k ϭ 3.5͒ and C-doped organosilicate glass ͑OSG, k ϭ 2.9). Experimental results indicate that FSG has a higher thermal stability ͑Ͼ600°C͒ than OSG ͑500°C͒, based on the results of thermal annealing for 30 min in an N 2 ambient. The degradation of the low-k property in OSG is mainly due to the thermal decomposition of methyl (ϪCH 3 ) groups at temperatures above 500°C. For the Cu gated oxide-sandwiched low-k dielectric metal-insulator-semiconductor ͑MIS͒ capacitors, Cu penetration was observed in both FSG and OSG after the MIS capacitors were bias-temperature stressed at 250 and 150°C, respectively, with an effective applied field of 0.8 MV/cm. Specifically, Cu appeared to drift more readily in OSG than in FSG, presumably because OSG has a more porous and less dense structure than FSG. The Cu permeation can be impeded by a thin nitride ͑SiN͒ barrier layer.

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A highly reliable self-planarizing low-k intermetal dielectric for sub-quarter micron interconnects

Cited by 10 publications

References 6 publications

Planarization Processes and Applications: I. Undoped GeO2 ‐ SiO2 Glasses

Planarization Processes and Applications: I. Undoped GeO2 ‐ SiO2 Glasses

Metal/fluorinated-dielectric interactions in microelectronic interconnections: Rapid diffusion of fluorine through aluminum

Physical and Electrical Characteristics of F- and C-Doped Low Dielectric Constant Chemical Vapor Deposited Oxides

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