Ultralarge scale (ULSI) integrated circuits invariably require more than one level of interconnect metal. One of the main challenges in implementing such multilevel interconnect structures is planarization of the intermetal dielectric. Planarity is needed in multilevel interconnect technology because smooth surfaces are required to ensure good metal step coverage, 1 and to provide a flat enough field, within lithographic depth of focus capabilities, such that contact vias and metal wires can be patterned. 2,3 Failure to provide planar surfaces in the dielectric can result in electrical defects, electromigration problems, impairment of device reliability, and yield reduction.Reflow of dielectric films has been effective to a degree in reducing local variations in topography of multilevel interconnections. Phosphorus-doped silicon dioxide, or phosphosilicate glass (PSG), and phosphorus-and boron-doped silicon dioxide, or borophosphosilicate glass (BPSG), reflow processes have been commonly used to obtain insulating films with reasonably flat surfaces. 1,4,5 These films exhibit profiles over steps that get progressively smoother with higher phosphorus and boron concentration, reflecting the corresponding enhancement in viscous flow. However, decreasing thermal budgets and increasing via aspect ratios as well as the requirement of strict control of the dopant concentration have caused a transition to an alternative method for achieving planar surfaces, chemical mechanical polishing (CMP).CMP has been proven to achieve a measure of global planarization not previously possible with spin-on and resist etchback techniques. 6 However, CMP processes are hampered by pattern sensitivities, which cause regions on a chip to have thicker dielectric layers than other regions due to differences in the underlying topography. 7 Also, inconsistencies in reproducing polishing rates have also proven to be a problem. In fact, CMP is performed with empirical polishing rates and timed polishes. This results in a decrease in reliability and yield, and is costly.Conceptually, a glass that could be planarized within thermal budget constraints and still maintain good stress, electrical, and water solubility properties could eliminate the need for some, if not all, CMP steps, especially the CMP step for the first dielectric layer between the devices and the first-level metal, i.e., the poly-metal dielectric (PMD). Boron and/or phosphorus-doped SiO 2 films are unable to incorporate sufficient quantities of the dopant elements to reflow at a sufficiently low temperature before the glasses become unstable. In order to push the reflow temperature lower with the goal of planarizing reflow, an alternative chemical system, such as, GeO 2 -SiO 2 discussed below, is needed.There are several literature reports on the properties of the GeO 2 -SiO 2 system. [8][9][10]11 Only one of these 11 deals with GeO 2 glass films compositions greater than 25 mol %. The limited range of germanosilicate (GeO 2 ) compositions explored in most of these studies is not, ...

Plasma enhanced chemical vapor deposition of boron and phosphorus doped mixed GeO2−SiO2 glass films in a horizontal tube reactor using germane false(GeH4false) , silane false(SiH4false) , diborane false(B2H6false) , phosphine false(PH3false) , and oxygen false(O2false) has been studied. The glass films offer the potential for both trench refilling and interlevel dielectric applications. Film synthesis was carried out at 200°C using a dual coil inductively coupled plasma system. Oxide film composition was determined using energy dispersive X‐ray spectroscopy and Auger energy spectroscopy. Cross‐sectional scanning electron microscopy was employed for studing the compositional dependency of the reflow behavior of the mixed GeO2−SiO2 , P2O5−GeO2−SiO2 , B2O3−GeO2−SiO2 , and P2O5−B2O3−GeO2−SiO2 glass films over silicon trenches under various ambient atmospheres. Reflow experiments were performed at temperatures ranging from 550 to 800°C in various gas ambient atmospheres. As result of the work, a low temperature (∼600°C) reflow process was developed resulting in fully planar dielectric films. This process may have application for planarization of interlevel dielectrics for ultralarge scale integrated circuits. © 1999 The Electrochemical Society. All rights reserved.

Glass films of undoped and boron and phosphorus doped GeO 2 -SiO 2 glass films were prepared by plasma enhanced chemical vapor deposition using germane, silane, phosphine, diborane, and oxygen as precursor gas sources with argon as a carrier gas. Film synthesis was carried out at 200ЊC using a dual-coil, inductively coupled plasma system. The presence of silane was not necessary to catalyze the decomposition of germane in the plasma environment as required in a strictly thermal environment. The index of refraction of undoped films changes linearly with SiO 2 composition, and deposition rate was nearly constant across all film compositions. Oxide film composition was determined using energy dispersive X-ray spectroscopy and Auger energy spectroscopy. For undoped films, solid-phase SiO 2 composition varied linearly with silane gas-phase composition. For doped compositions, phosphorus mole fraction in the solid phase was up to a factor of two greater than that present in the gas phase. In contrast to this, the quantity of boron incorporated into the solid phase was a factor of five to six less than present in the gas phase. When both dopants were present in the gas phase, the amount of each incorporated into the solid phase was similar to that in the gas phase. Figure 1. PECVD cross-flow deposition apparatus.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 132.174.255.116 Downloaded on 2015-03-09 to IP ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 132.174.255.116 Downloaded on 2015-03-09 to IP

New and emerging process technologies such as Damascene interconnect, metal gate and metal silicide processes are creating metal contamination control challenges for current and future generations of integrated circuits. In this work, we studied the contamination of oxidized silicon wafers by several metals of industrial importance including copper, cobalt, sodium, iron and nickel. Contamination was applied by spin-coating in a range from 20ppb to 500 ppb. Such levels are representative of exposure challenges induced during chemical processes such as CMP (chemical mechanical planarization) cleans. Solvated contamination ions were driven into the oxide layer by corona temperature stress (CTS). The concentrations of metallic species incorporated within the oxide by CTS were quantified using VPD-ICPMS (vapor phase decomposition) and SIMS (secondary ion mass spectrometry) surface analysis techniques. Noncontact COCOS (Corona Oxide Characterization of Semiconductor) methods were employed to measure the electrical properties and reliability of nascent and contaminated oxide/silicon structures. We show that in the absence of significant signals from the surface analysis techniques the COCOS methods show signatures of the metallic contamination in the measurement results.

No abstract