A Highly Threshold Voltage-Controllable 4T FinFET with an 8.5-nm-Thick Si-Fin Channel

Liu, Yongxun; Masahara, Meishoku; Ishii, Keisuke; Sekigawa, Toshihiro; Takashima, H.; Yamauchi, H.; Suzuki, Eiichi

doi:10.1109/led.2004.831205

Cited by 119 publications

(57 citation statements)

References 12 publications

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“…However, it is very difficult to control Vth by tuning the gate work function in FinFETs because of inseparable gate as shown in Fig. 1 [34]. So, here we have discussed about Vth control by adjusting the fin height.…”

Section: A Effect Of Hfinmentioning

confidence: 99%

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

Mohapatra¹,

Pradhan²,

Singh³

et al. 2015

IEEE Trans. Nanotechnology

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Now a days FinFETs integrated into complex circuit applications can fulfill the demand of smartphones and tablets for better performance and make chips that can compute faster. This work studies the impact of HFin and WFin variations on various performance matrices including static as well dynamic figures of merit (FOMs). With the help of Aspect Ratio (WFin/HFin). The device is branched into three parts i.e., FinFET, Trigate, and Planar MOSFET. This unique report is a presentation of a detailed analysis about the impact of fin height (HFin) and width (WFin) on various performances including the DC as well as AC figures of merit (FOMs). The static or low frequency performances like threshold voltage (Vth), on current (Ion), off current (Ioff), power dissipation, transconductance (gm), output conductance (gd), transconductance generation factor (TGF=gm/ID), early voltage (VEA), gain (AV) and dynamic or high frequency performances as gate capacitance (Cgg), cutoff frequency (fT), output resistance (R0), intrinsic delay are systematically presented with the variation of device geometry parameters. The results presented in this report can be of great help to device engineers in designing 3-D devices as per their requirement.A 1536-125X (c)

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Section: A Effect Of Hfinmentioning

confidence: 99%

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

Mohapatra¹,

Pradhan²,

Singh³

et al. 2015

IEEE Trans. Nanotechnology

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show abstract

“…There have been several previous developments for separated DG MOSFETs-the "flexible threshold voltage FinFET" [10], the "four-terminal FinFET" [11], and the "independent double gate" [12], [13]. One of the advantages of separated DG MOSFETs is a greater degree of freedom in the adjustment of the threshold voltage by applying a designed bias to one of the separated gates.…”

Section: Threshold Voltage For Separated Dg Mosfetsmentioning

confidence: 99%

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

Han¹,

Kim²,

Choi³

2008

IEEE Trans. Electron Devices

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“…So far, we have developed the simple fabrication technique of Si-fin channels with an ideal rectangular cross section [12]- [16] and ultrathin vertical Si walls [20], [21] using the orientation-dependent wet etching, and we demonstrated the excellent electrical characteristics of the n poly-Si gate n-channel FinFETs. In the n poly-Si gate n-channel FinFETs in the previous works, however, the was not managed and actually showed a negative value of V. The main target of this work is to develop the TiN gate FinFET with a proper .…”

Section: Fabrication Processesmentioning

confidence: 99%

“…Through the multi-fin hard masks, the SOI layer was etched with a 2.38% tetramethylammonium hydroxide (TMAH) solution at 50 C for 1 min. Since the sidewalls of the Si-fins have a (111)-oriented plane with an extremely low etch rate in the TMAH compared with other planes, the very narrow and straight Si-fin channels can be fabricated [12]- [16]. After a 2.2-nm-thick gate oxide formation, the TiN film as a gate material was deposited on some wafers by using the conventional reactive sputtering at 1 Pa, and an n poly-Si layer was deposited on the other wafers.…”

Section: And Psgmentioning

confidence: 99%

Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

Liu

Kijima

Sugimata

et al. 2006

IEEE Trans. Nanotechnology

107

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The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN ( TiN ) slightly decreases with increasing nitrogen (N 2 ) gas flow ratio, = N 2 (Ar + N 2 ) in the sputtering, from 17% to 100%. The experimental threshold voltage ( th ) dependence on the shows that the more offers the lower th for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different showed that the more amount of nitrogen is introduced into the TiN films with increasing , which suggests that the lowering of TiN with increasing should be related to the increase in nitrogen concentration in the TiN film. The desirable th shift from 0.22 to 0.22 V was experimentally confirmed by fabricating n + poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TiN gate FinFET fabrication.

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A Highly Threshold Voltage-Controllable 4T FinFET with an 8.5-nm-Thick Si-Fin Channel

Cited by 119 publications

References 12 publications

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

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