A Hybrid Dry-Wet Approach for Removal of a Dummy Polysilicon Gate in a Replacement Metal Gate Scheme

Abstract

Beginning at the 45nm node, the semiconductor industry is moving to high-k gate dielectrics and metal gate electrodes for CMOS logic devices [. Although different approaches of building these devices are being pursued, most of the industry has consolidated behind a gate last approach, in which the transistor is built around a dummy poly polysilicon gate, which is subsequently removed and replaced with a metal gate. Current approaches to removing the dummy poly gate include plasma-based dry processes and liquid-phase wet etching.

Dummy Poly Gate Removal Scheme at FinFET

“…Fig 3 is the result of partial etch performance on one commercial ICP etcher. [11] It is demonstrated that high current leakage occurred at longer dry etch process time. In 85S and 100S cases, polysilicon was completely removed by dry etching.…”

“…However, this approach requires more complex process engineering at 3D structure. Both perfect physical structure and good electronic performance are challenging for dummy poly gate removal process [1][2][3][4][5][6]. As is well known, both dry etching and wet etching can effectively remove polysilicon.…”

“…However, this scheme could NOT fully avoid the disadvantage of both wet etching and dry etching, such as PID to degrade the device performance, ILD/SiN spacer loss, and the discontinuous sidewall profile. Besides, it's too short queue -time and lower throughput are also the concerns [2]. We introduced one full dry etching scheme to remove dummy gate polysilicon at FinFET.…”