2008 International Conference on Reconfigurable Computing and FPGAs 2008
DOI: 10.1109/reconfig.2008.23
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A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors

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Cited by 4 publications
(1 citation statement)
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“…A significant amount of research is engaged with comparisons of the architectures FPGAs, GPUs, and CPUs, and the determination of what problem domains of parallel processing that suits which architecture better (see, e.g., [9]). Previously, some of the processing stages of the system described in this paper have been realized on FPGAs [23,25], and we recognize that there are problem domains in the field of parallel processing, where the FPGA would be the better choice for performance. However, the actual development costs connected to the complexity of FPGA programming as well as the high price of a sufficiently powerful FPGA in combination with the reduced flexibility in respect to code changes connected to required adaptations made FPGAs a less favorable solution in our case.…”
Section: Introductionmentioning
confidence: 99%
“…A significant amount of research is engaged with comparisons of the architectures FPGAs, GPUs, and CPUs, and the determination of what problem domains of parallel processing that suits which architecture better (see, e.g., [9]). Previously, some of the processing stages of the system described in this paper have been realized on FPGAs [23,25], and we recognize that there are problem domains in the field of parallel processing, where the FPGA would be the better choice for performance. However, the actual development costs connected to the complexity of FPGA programming as well as the high price of a sufficiently powerful FPGA in combination with the reduced flexibility in respect to code changes connected to required adaptations made FPGAs a less favorable solution in our case.…”
Section: Introductionmentioning
confidence: 99%