A hybrid Nano/CMOS dynamically reconfigurable system—Part II

Jha

2015

IEEE Trans. VLSI Syst.

Self Cite

Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density and save area. Because logic folding reduces area significantly, most of the on-chip communications become localized. To take full advantage of localized communications, we then presented a new CMOS-based fine-grain dynamically reconfigurable (FDR) architecture. It consists of an array of homogeneous logic elements (LEs), which can be configured into logic or interconnect or a combination of both. FDR eliminates most of the long-distance and global wires, which occupy a large amount of area in conventional FPGAs. FDR improves the areadelay product by an order of magnitude relative to conventional architectures. In this paper, we present an augmented FDR 2.0 architecture, where: 1) the LE is augmented with dedicated carry logic to facilitate arithmetic operations; 2) diagonal direct links are incorporated to improve the flexibility of local communication; and 3) coarse-grain blocks, including embedded memories and digital signal processing (DSP) blocks, are added to support fast data-intensive computations. Experimental results show that the coarse-grain design can improve circuit performance by 3.6× compared with the fine-grain FDR architecture. Incorporation of the DSP blocks in FDR 2.0 also enables more effective areadelay and power-delay tradeoffs, allowing the users to trade performance for smaller area or power consumption. We have implemented the design in the 22-nm FinFET technology, which enables more flexible and effective power management. Finally, different types of FinFETs and power management techniques have been explored in FDR 2.0 to optimize power.

Section: Fdrmapmentioning

confidence: 99%

“…8 shows the LE design with dedicated carry logic. With the design space explorations presented in [5], we select the LE design parameter values as follows: (l, n, F s_LE , F o , F i ) = (4, 16,12,8,12). The carry unit shares the same four inputs with the LUT.…”

Section: Augmented Fine-grain Le Array In Fdr 20mentioning

confidence: 99%

FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation

Lin

Jha

2015

IEEE Trans. VLSI Syst.

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“…An automatic tool, NanoMap [9], takes register-transfer level (RTL) or gate-level netlists specified in Verilog/VHDL, and generates the configuration bitmaps of NATURE. It integrates the logic folding feature and identifies the best folding level based on user-specified optimization goals and constraints.…”

Section: B Naturementioning

confidence: 99%

SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs

Lin

Jha

2012

IEEE Trans. VLSI Syst.

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We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was based on CMOS logic and nano RAMs. It used the concept of temporal logic folding and fine-grain (e.g., cycle-level) dynamic reconfiguration to increase logic density by an order of magnitude. This dynamic reconfiguration is done intra-circuit rather than inter-circuit. However, the previous design of NATURE required fine-grained distribution of nano RAMs throughout the field-programmable gate array (FPGA) architecture. Since the fabrication process of nano RAMs is not mature yet, this prevents immediate exploitation of NATURE. In this paper, we present a NATURE architecture that is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. We use fast and low-power SRAM blocks that are based on 10T SRAM cells. We have also laid out the various FPGA components in a 65-nm technology to evaluate the FPGA performance. We hide the dynamic reconfiguration delay behind the computation delay through the use of shadow SRAM cells. Experimental results show more than an order of magnitude improvement in logic density and 3 48 improvement in the area-delay product relative to a traditional baseline FPGA architecture that does not use the concept of logic folding.Index Terms-Field-programmable gate arrays (FPGAs), integrated circuits, logic folding, nanotechnology reconfigurable architecture (NA-TURE).

“…NATURE also supports reconfiguration of coarse-grained DSP blocks [11] and block RAMs (BRAMs) at similar speeds, making high frequency context switches feasible to improve area utilization and energy efficiency. The custom mapping tool, NanoMap [15], maps a circuit netlist to the architecture and generates the context switching controls automatically for each occupied logic element (LUTs, DSPs, and others), which together describe the circuit.…”

Section: Introductionmentioning

confidence: 99%

Fracturable DSP Block for Multi-context Reconfigurable Architectures

Warrier

Shreejith

Circuits Syst Signal Process

et al. 2016

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Multi-context architectures like NATURE enable low-power applications to leverage fast context switching for improved energy efficiency and lower area footprint. The NATURE architecture incorporates 16-bit reconfigurable DSP blocks for accelerating arithmetic computations, however, their fixed precision prevents efficient re-use in mixed-width arithmetic circuits. This paper presents an improved DSP block architecture for NATURE, with native support for temporal folding and run-time fracturability. The proposed DSP block can compute multiple sub-width operations in the same clock cycle and can dynamically switch between sub-width and full-width operations in different cycles. The NanoMap tool for mapping circuits onto NA-TURE is extended to exploit the fracturable multiplier unit incorporated in the DSP block. We demonstrate the efficiency of the proposed dynamically fracturable DSP block by implementing logic-intensive and compute-intensive benchmark applications. Our results illustrate that the fracturable DSP block can achieve a 53.7% reduction in DSP block utilization and a 42.5% reduction in area with a 122.5% reduction in power-delay product without exploiting logic folding. We also observe an average reduction of 6.43% in power-delay product for circuits that utilize NATURE's temporal folding compared to the existing full precision DSP block in NATURE, leading to highly compact, energy efficient designs.