A hybrid radix-4/madix-8 low power signed multiplier architecture

Cherkauer, B.S.; Friedman, Eby G.

doi:10.1109/82.618039

Cited by 31 publications

(21 citation statements)

References 18 publications

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“…Another technology to mitigate the delay penalty associated with the generation of 3B for the Booth-3 architecture is a hybrid radix-4/radix-8 multiplier architecture [11] which generates 3B by a high speed 64-bit adder in parallel with the reduction of the Booth-2 PPs. In [11], as the radix-8 PPs are not available until three Booth-2 PP reduction steps have been completed, fewer bits in parallel are available at the start of the reduction process.…”

Section: Hybrid Radix-4/radix-8 Multiplier Architecture Using Pamentioning

confidence: 99%

“…As a result, the delay introduced by multiple generation is minimized, but the number of bits which need to be summed in the reduction tree is increased. Brian et al [11] introduced another multiplier architecture that uses a combination of Booth-2 and Booth-3 encoding to mitigate the delay penalty associated with the generation of hard multiples for the Booth-3 architecture.…”

Section: Introductionmentioning

confidence: 99%

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A Hybrid Multiplier Architecture Using Partially Redundant Booth Algorithm

Liu

Liang

Shao

et al. 2007

2007 International Workshop on Electron Devices and Semiconductor Technology (EDST)

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In the conventional hybrid Booth multiplier architecture, the reduction of the radix-8 partial products begins after the generation of three times the multiplicand has been performed by a wide bit widths adder in parallel with the reduction of the radix-4 partial products. Thus, the reduction process is not as time efficient. To solve this problem, we propose a novel hybrid multiplier architecture utilizing partially redundant radix-8 Booth encoding to generate three times the multiplicand. Experiments show that this novel hybrid multiplier architecture requires 2.8% smaller area and 4.2% less power with the almost same delay for a 64x64-bit multiplier as compared with a radix-4 implementation. The novel hybrid radix-4/radix-8 architecture is therefore a compromise between high speed and low power.

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Section: Hybrid Radix-4/radix-8 Multiplier Architecture Using Pamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Hybrid Multiplier Architecture Using Partially Redundant Booth Algorithm

Liu

Liang

Shao

et al. 2007

2007 International Workshop on Electron Devices and Semiconductor Technology (EDST)

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“…Earlier designs have employed various architecture and circuit-level optimizations to reduce array multiplier latency and increase its throughput [18,20,22,28]. However, there is relatively much less work on improving the energy efficiency of multiplier datapath [5], which is one of our primary contributions.…”

Section: B Synchronous Floating-point Multipliersmentioning

confidence: 99%

“…Traditionally, high performance has been the key driving factor in multiplier design. However, as power consumption has become a major design constraint lately, a number of low-power multiplier designs have been proposed both in synchronous [5,11] and asynchronous domains [9,12,13].…”

Section: Multiplier Design Trade-offsmentioning

confidence: 99%

An Asynchronous Floating-Point Multiplier

Sheikh

Manohar

2012

2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems

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Abstract-We present the details of our energy-efficient asynchronous floating-point multiplier (FPM). We discuss design trade-offs of various multiplier implementations. A higher radix array multiplier design with operand-dependent carrypropagation adder and low handshake overhead pipeline design is presented, which yields significant energy savings while preserving the average throughput. Our FPM also includes a hardware implementation of denormal and underflow cases. When compared against a custom synchronous FPM design, our asynchronous FPM consumes 3X less energy per operation while operating at 2.3X higher throughput. To our knowledge, this is the first detailed design of a high-performance asynchronous IEEE-754 compliant double-precision floating-point multiplier.Keywords-Floating point arithmetic; asynchronous logic circuits; very-large-scale integration; pipeline processing I. INTRODUCTION Energy-efficient floating-point computation is important for a wide range of applications. Traditionally, VLSI designers primarily relied on CMOS technology and voltage scaling to reduce power consumption [4]. With the transistor threshold voltage fixed [10], V DD has been scaling very slowly if at all, which means all performance improvements come at an increased energy consumption. Furthermore, process variations in deep sub-micron range have made devices far less robust, which is increasingly making it difficult for synchronous designers to overcome the problems associated with clock skew rates and clock distribution [6]. The findings of a recent in-depth study, to explore and devise ways to further scale supercomputer petaFLOP performance by 1000X, indicate the inadequacy of current design practices and technologies to achieve the desired throughput within a sustainable power budget [1]. This underscores a pressing need for alternate design practices, to reduce energy consumption for floating-point computations while preserving robust behavior in advanced technology nodes.At the other end of the spectrum, embedded systems that have traditionally been considered low performance are demanding higher and higher throughput for the same power budget to support compute-intensive floating-point applications that improve the user experience. Since these applications have to be deployed on portable devices with limited batterylife, it is critical that we develop energy-efficient floatingpoint hardware for these embedded systems, not simply high performance floating-point hardware.The IEEE 754 standard [19] for binary floating-point arithmetic provides a precise specification of floating-point number formats, computation operations, and exceptions and their handling. The combination of a vast range of inputs, special cases, and rounding modes makes the hardware implementation of fully IEEE 754 standard compliant floating-point arithmetic a very challenging task. Ignoring certain aspects of the standard can lead to unexpected consequences in the context of numerical algorithms. Hence, most floating-point hardware is IEEE-comp...

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“…A solution for non-pipelined multipliers is the hybrid radix-4/radix-8 architecture presented in 16 . In this scheme, radix-4 and radix-8 partial products are performed in parallel, reducing by 13% the power with a 9% increase in delay, as compared with a radix-4 implementation.…”

Section: 11mentioning

confidence: 99%

Efficient hardware implementation of 3X for radix-8 encoding

Ruiz

Granda

2007

SPIE Proceedings

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Several commercial processors have selected the radix-8 multiplier architecture to increase their speed, thereby reducing the number of partial products. Radix-8 encoding reduces the digit number length in a signed digit representation. Its performance bottleneck is the generation of the term 3X, also referred to as hard multiple. This term is usually computed by an adding and shifting operation, 3X=2X+X, in a high-speed adder. In a 2X+X addition, close full adders share the same input signal. This property permits simplified algebraic expressions associated to a 3X operation other than in a conventional addition. This paper shows that the 3X operation can be expressed in terms of two signals, H i and K i , functionally equivalent to two carries. H i and K i are computed in parallel using architectures which lead to an area and speed efficient implementation. For the purposes of comparison, implementation based on standard-cells of conventional adders has been compared with the proposed circuits based on these H i and K i signals. As a result, the delay of proposed serial scheme is reduced by roughly 67% without additional cost in area, the delay and area of the carry look-ahead scheme is reduced by 20% and 17%, and that of the parallel prefix scheme is reduced by 26% and 46%, respectively.

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A hybrid radix-4/madix-8 low power signed multiplier architecture

Cited by 31 publications

References 18 publications

A Hybrid Multiplier Architecture Using Partially Redundant Booth Algorithm

A Hybrid Multiplier Architecture Using Partially Redundant Booth Algorithm

An Asynchronous Floating-Point Multiplier

Efficient hardware implementation of 3X for radix-8 encoding

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