A D-Band High-Gain and Low-Power LNA in 65-nm CMOS by Adopting Simultaneous Noise- and Input-Matched G
 max-Core

Yun, Byeonghun; Park, Dae‐Woong; Mahmood, Hafiz Usman; Kim, Doyoon; Lee, Sang‐Gug

doi:10.1109/tmtt.2021.3066972

Cited by 40 publications

(3 citation statements)

References 38 publications

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“…5 analyzes the proposed wideband RF amplifiers. For both PA and RF VGAs, a common source topology with resistive feedback at the input and output stages, and a common source topology with inductive feedback at intermediate stages [66], [67], [68] are used. The inductive feedback topology could boost power gain at the millimeter frequency band, which is known as the maximum achievable gain [66].…”

Section: B Wideband Rf Pa and Rf Vgamentioning

confidence: 99%

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression

Wang,

Abdo,

Liu

et al. 2024

IEEE J. Solid-State Circuits

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A sub-THz (88-136 GHz) full-duplex (FD) phasedarray transceiver (TRX) integrating an RF self-interference (SI) canceller with differential feeding FD antennas is presented in this work. The LO phase generation chain controls differential transmitter outputs for the phased-array operation. The differential feeding FD antenna with differential pairs of chips achieves over 35-dB SI suppression. The SI suppression is improved by 20 dB when the SI canceller is turned on. Without any digital-domain SI cancellation (SIC), a total SI suppression of >60 dB is achieved over a 2-GHz bandwidth. The proposed neutralized mixer with over 20-dB LO feedthrough suppression and wideband RF amplifiers support a large data rate at sub-THz frequencies. This is the world's first demonstrated sub-THz FD phased-array TRX. In the over-the-air (OTA) measurements for FD mode, the proposed FD TRX achieves 6 Gb/s in 8PSK and 4 Gb/s in 16QAM. It also achieves a 112-Gb/s data rate for OTA TX-to-RX.

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Section: B Wideband Rf Pa and Rf Vgamentioning

confidence: 99%

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression

Wang,

Abdo,

Liu

et al. 2024

IEEE J. Solid-State Circuits

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“…The Gmax condition is achieved by adding linear-losslessreciprocal embedded components to the single transistor [18]. These embedded components come from using two or three passive circuits at the gate, drain, and source nodes [18], [22]. As shown in Fig.…”

Section: A Operation Principle At Fundamental Frequencymentioning

confidence: 99%

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

et al. 2023

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This article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (Gmax) by adding embedded passive components, thereby obtaining high voltage swings. Then, the transistor's nonlinearity is essential, which is maximized by the harmonic transition scheme of the transistor operation along with high voltage swings. In addition, a harmonic reflector and a harmonic leakage canceller are employed for the second harmonic enhancement. The harmonic reflector prevents unwanted harmonic mixing by minimizing the incoming second harmonic current fed back to the input. The harmonic leakage canceller suppresses the leakage loss of the second harmonic current present at the output. Furthermore, thanks to a proposed dual-band output matching network, the output impedance is conjugately matched to achieve the Gmax at the fundamental frequency while it is matched to extract the second harmonic output power simultaneously. To verify the proposed techniques, the prototype was designed as a single-stage circuit that does not require additional amplifying stages, which led to higher power efficiency and lower chip area. Implemented in a 65-nm CMOS process, the measurement results show a saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237−263 GHz), respectively, while requiring a chip area of 0.071 mm 2 . Total power efficiency, including the effect of injected signal power, is 2.87 % while consuming only 37 mW dc power.

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“…T HERE is an increasing demand for higher data rates and lower latency in the wireless communication. This has pushed for increasing design efforts in the subterahertz frequency bands due to their higher available bandwidths [1], [2] and compound semiconductors due to their higher cut off frequencies [3], [4] and superior power handling capabilities [5]- [9]. Architectures with heterogeneous integration of integrated circuits (ICs) are being proposed with front-end circuits preferably in III-V technologies such as InP and GaN [6], [7].…”

Section: Introductionmentioning

confidence: 99%

A 120–140-GHz LNA in 250-nm InP HBT

Chauhan¹,

Collaert

Wambacq

2022

IEEE Microw. Wireless Compon. Lett.

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A D-Band High-Gain and Low-Power LNA in 65-nm CMOS by Adopting Simultaneous Noise- and Input-Matched G _max-Core

Cited by 40 publications

References 38 publications

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

A 120–140-GHz LNA in 250-nm InP HBT

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A D-Band High-Gain and Low-Power LNA in 65-nm CMOS by Adopting Simultaneous Noise- and Input-Matched G max-Core

Cited by 40 publications

References 38 publications

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

A 120–140-GHz LNA in 250-nm InP HBT

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A D-Band High-Gain and Low-Power LNA in 65-nm CMOS by Adopting Simultaneous Noise- and Input-Matched G _max-Core