A K/Ka/V Triband Single-Signal-Path Receiver With Variable-Gain Low-Noise Amplifier and Constant-Gain Phase Shifter in 28-nm CMOS

Liang, Chia-Jen; Zhang, Yan; Chiang, Ching-Wen; Huang, Ruijie; Zhou, Jia; Du, Jieqiong; Wen, Kuei-Ann; Chang, M.F.; Kuan, Yen-Cheng

doi:10.1109/tmtt.2021.3061707

Cited by 8 publications

(3 citation statements)

References 37 publications

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“…However, for each quadrant, only two different gains need to be controlled, so by switching the DAC that controls each gain, only two DACs are needed. This technique is commonly used to reduce the number of DACs needed [ 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 ].…”

Section: State-of-the-art and Proposed Vector Modulatormentioning

confidence: 99%

A 17.8–20.2 GHz Compact Vector-Sum Phase Shifter in 130 nm SiGe BiCMOS Technology for LEO Gateways Receivers

Pino

Khemchandani

San-Miguel-Montesdeoca³

et al. 2023

Micromachines

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This paper presents a novel and compact vector modulator (VM) architecture implemented in 130 nm SiGe BiCMOS technology. The design is suitable for use in receive phased arrays for the gateways of major low Earth orbit (LEO) constellations that operate in the 17.8 to 20.2 GHz frequency range. The proposed architecture uses four variable gain amplifiers (VGA) that are active at any given time and are switched to generate the four quadrants. Compared to conventional architectures, this structure is more compact and produces double the output amplitude. The design offers 6-bit phase control for 360°, and the total root mean square (RMS) phase and gain errors are 2.36° and 1.46 dB, respectively. The design occupies an area of 1309.4 μm × 1783.8 μm (including pads).

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Section: State-of-the-art and Proposed Vector Modulatormentioning

confidence: 99%

A 17.8–20.2 GHz Compact Vector-Sum Phase Shifter in 130 nm SiGe BiCMOS Technology for LEO Gateways Receivers

Pino

Khemchandani

San-Miguel-Montesdeoca³

et al. 2023

Micromachines

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“…In particular, in the beamforming system, sophisticated phase variation is recognized as an essential technology. Therefore, various structures of phase shifters have already been introduced [4][5][6], and research to improve the performance of phase shifters is still actively underway.…”

Section: Introductionmentioning

confidence: 99%

Design Technique of K-Band CMOS Phase Shifter with L-C-L T-Type Low Pass Structure

Jang,

Kim,

Park

2023

Electronics

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In this study, we designed a 5-bit K-band CMOS switch type phase shifter. In order to minimize phase and gain errors, a design technique for bits constituting the phase shifter was proposed. The proposed design technique has been achieved by adjusting the resonant frequencies of inductance and capacitance in the L-C-L T-type low pass filter structure. Through this, a method of optimizing the phase shifter with the T-type low pass filter structure was presented. The K-band 5-bit phase shifter was designed with a 65 nm CMOS process to verify the feasibility of the proposed design technique. The core size was 0.78 × 0.21 mm2. At the frequency ranges of 22.0 to 23.0 GHz, the insertion loss and RMS phase and gain errors were measured to be 7.44 ± 2.0 dB, 2.6°, and 1.2 dB, respectively.

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“…We expect to achieve a low noise figure, a modest gain, high linearity, and low power consumption for LNAs to extend the dynamic range and increase the receiver system's sensitivity, which adds to the LNA design challenges. In recent decades exhaustive research has been done on wideband LNAs [1]. The most promising topology used to realize the ultra-wideband LNA is a Distributed amplifier (DA) [2].…”

Section: Introductionmentioning

confidence: 99%

A K/Ka-Band Switchless Reconfigurable 65 nm CMOS LNA Based on Suspended Substrate Coupled Line

et al. 2022

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This article presents a K/Ka (18-40) GHz dual-band switch-free reconfigurable 65nm CMOS Low-Noise Amplifier (LNA) realized by inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL) for the first time to the author's best knowledge. The amplified input signal from the broadband drive stage is divided into two parallel single band stages by the proposed inter-stage SSCL. Two split-band signals are amplified by the corresponding High-band (Ka) and Low-band (K) stages. The proposed outputstage SSCL combines the amplified two single-bands at the output. The proposed SSCL also provides the required network matching to the LNA. The single band of operation can be achieved by simply turning off the unused transistor band's drain voltage. The proposed LNA achieves a maximum noise figure (NF) taken in dual-mode of 1 dB and 1.2 dB and a gain of 27 dB with 0.2 dB and 2 dB variation in the K-band and Kaband, respectively. Statistical analysis and design of experiment (DoE) are applied to predict the percentage error tolerance and validate the contribution of the parameters towards gain, return loss, and noise figure. This LNA exhibits an input and output 1-dB compression point (IP1dB & OP1dB), third-order input & output intercept point (IIP3 & OIP3) of -17/-16 dBm, +7.1/6.4 dBm, 0 dBm and +25/+23 dBm over 18-24/25-40 GHz respectively. The fabricated LNA draws 21.4 mA from 1.2 V with a size of 0.61×0.92 mm 2 .

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A K/Ka/V Triband Single-Signal-Path Receiver With Variable-Gain Low-Noise Amplifier and Constant-Gain Phase Shifter in 28-nm CMOS

Cited by 8 publications

References 37 publications

A 17.8–20.2 GHz Compact Vector-Sum Phase Shifter in 130 nm SiGe BiCMOS Technology for LEO Gateways Receivers

A 17.8–20.2 GHz Compact Vector-Sum Phase Shifter in 130 nm SiGe BiCMOS Technology for LEO Gateways Receivers

Design Technique of K-Band CMOS Phase Shifter with L-C-L T-Type Low Pass Structure

A K/Ka-Band Switchless Reconfigurable 65 nm CMOS LNA Based on Suspended Substrate Coupled Line

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