A Ku-Band GaAs Multifunction Transmitter and Receiver Chipset

Abstract

This paper presents a Ku-band monolithic multifunction transmitter and receiver chipset fabricated in 0.25-μm GaAs pseudomorphic high-electron mobility transistor technology. The chipset achieves a high level of integration, including a 4-bit 360° digital phase shifter, 5-bit 15.5-dB digital attenuator, amplifier and 9-bit digital serial-to-parallel converter for digital circuit control. Since the multifunction chipset includes a medium power amplifier and a low-noise amplifier, it features high P1dB and low noise figures over the full Ku-band frequencies. The multifunction transmitter shows a peak gain of 16.5 dB with output P1dB of 19.2 dBm at 15 GHz. The multifunction receiver shows a peak gain of 17.3 dB with noise figure of 2.5 dB at 15 GHz. The attenuation range is 15.5 dB with a step of 0.5 dB and the phase shift range is 360° with a step of 22.5°. Each chip area of the transmitter and receiver is 4.2 × 2.8 mm2.

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

“…Along with the number of bits, the designation of the bits within the core-chip is reported, when available: clearly, most of the bits are used for the phase and amplitude control, while, depending on the chip functionalities, up to six bits [15] are adopted for the switches. It is worth to note than in several cases [16][17][18][19] a serial output bit is also available, allowing to connect more CCs in daisy chain and configure them sequentially, and/or to test/monitor the SIPO output. In principle, it is sufficient to route the last bit to an output pad, possibly after level shifting/buffering as in [17].…”

“…This choice is surely the most convenient in terms of design effort and modularity, since, once the DFF cell is optimized, it is just replicated 2n times to create the two n-bit registers. However, in order to reduce the overall transistor count, hence reducing chip area occupation and improving yield, the HR can be implemented with simple D-type latches in place of flipflops as in [15,19,28]. Since latches are sensitive to levels rather than transitions, in order to adopt this solution the load command must be given in the form of a short enable pulse rather than a transition as discussed in Section 6.…”

“…(b) Level shifter with common source buffer, adopted for example in [15]. (c) Level shifter with source follower buffer, adopted for example in [19]. Note that in all schemes diodes can be replaced by diode-connected transistors.…”

“…For example, in [15] two buffer stages have been adopted with the second stage's transistor twice as large as that of the first stage, to ensure fast commutation and preserve input signal polarity. In [19] an interesting solution is proposed where the level shifting and the (non-inverting) buffering functions are merged together by adopting an E-mode source-follower buffer along with translating diodes and a D-mode active pull-down, as reported in Figure 5c.…”

“…The latter is typically implemented with D-mode devices, hence requiring negative voltages. In [15,19,31] different examples of output buffer are presented, with or without diodes. The best topological solutions for the I/O interfaces are highly dependent on the specific input/output dynamics of the CC under development.…”