A leading-edge 0.9µm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling

Abstract

IntroductionPixel scaling trend on CMOS image sensor (CIS) calls for a novel technology to improve sensor's optical response being blocked or interfered by metal layers in traditional front-side illumination (FSI) sensor structure. Recently, backside illumination (BSI) sensor technology gradually becomes the main-stream CIS process to achieve virtually 100% fill-factor to boost the optical response and enhance optical angular response due to a shorter optical path. In this paper, a leading-edge N65 0.9μm pixel BSI technology using 300mm bulk silicon wafer is reported with process breakthroughs. Challenges for pixel-size scaling beyond 0.9μm are discussed. Technology OverviewBuilding image sensors with a BSI technology is an effective approach to maintain pixel size scaling trend without sacrificing sensor performance [1][2][3][4]. For pixel sizes less than ~1.75μm, BSI sensor's optical parameters, such as sensitivity, quantum efficiency (QE), optical cross-talk, angular response etc., can be significantly improved over FSI's due to no optical diffraction or blocking effect by routing metal layers along the optical path. Despite of the simple concept to flip the physical sensor with metal structure upside-down, developing the BSI manufacturing process is not a trivial task. Several key process modules that did not exist in traditional IC processes were created and carefully controlled to achieve mass-production capability. The following are the descriptions of the BSI processing and the related module performance.A schematic of BSI process flow is shown in Fig.1. P/P+ epi wafers provide a cost-effective solution compared with SOI wafers. After Back-End-of-Line (BEOL) process is completed, a device wafer runs through a planarization process and is bonded with a carrier wafer. The bonded wafer is then mechanically and chemically thinned down from the bottom side of the device wafer to the target thickness. The new backside Si surface is implanted with a shallow P+ layer followed by laser anneal for dopant activation. Backside antireflection (BARC) layers are coated to further enhance optical sensitivity. Pad opening, color filter array, and packaging process are performed to complete the BSI sensor manufacturing.The aforementioned process utilizes several new tools uncommon to traditional CMOS technology and that poses certain challenges in the process development. The major steps are wafer bonding, thin-down process, and laser anneal. Wafer bonding mainly determines the maximum mechanical stress the BSI wafers can tolerate in following processes including thermal treatment and packaging. It also imposes a certain stress to the bonded device and carrier wafers. Bond voids at the bonding interface and wafer distortion are key parameters of the bonding process. Fig. 2 shows a bonding process window obtained to achieve voidfree and good distortion. Optimized with a bond anneal process, 300mm wafers have been proven to withstand complete BSI process, color filter array (CFA), and packaging.For wafer thin-down process, f...

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