Electron cyclotron resonance plasmas have been used to produce the most effective, shortest time plasma hydrogenation of thin-film polycrystalline silicon transistors yet reported. We demonstrate that significant improvement in device characteristics can be achieved with these plasmas using exposure times of the order of only 1 min and that 5 min exposures give saturated characteristics of a 2 V threshold voltage, a 65 cm2/V s mobility, and a 107 on/off ratio. We also explore the pressure and power level dependence of this passivation, as well as the effects of shielding with a grid, and show that the more efficient and more stable electron cyclotron resonance hydrogen exposures are at lower pressures.

IntroductionPixel scaling trend on CMOS image sensor (CIS) calls for a novel technology to improve sensor's optical response being blocked or interfered by metal layers in traditional front-side illumination (FSI) sensor structure. Recently, backside illumination (BSI) sensor technology gradually becomes the main-stream CIS process to achieve virtually 100% fill-factor to boost the optical response and enhance optical angular response due to a shorter optical path. In this paper, a leading-edge N65 0.9μm pixel BSI technology using 300mm bulk silicon wafer is reported with process breakthroughs. Challenges for pixel-size scaling beyond 0.9μm are discussed. Technology OverviewBuilding image sensors with a BSI technology is an effective approach to maintain pixel size scaling trend without sacrificing sensor performance [1][2][3][4]. For pixel sizes less than ~1.75μm, BSI sensor's optical parameters, such as sensitivity, quantum efficiency (QE), optical cross-talk, angular response etc., can be significantly improved over FSI's due to no optical diffraction or blocking effect by routing metal layers along the optical path. Despite of the simple concept to flip the physical sensor with metal structure upside-down, developing the BSI manufacturing process is not a trivial task. Several key process modules that did not exist in traditional IC processes were created and carefully controlled to achieve mass-production capability. The following are the descriptions of the BSI processing and the related module performance.A schematic of BSI process flow is shown in Fig.1. P/P+ epi wafers provide a cost-effective solution compared with SOI wafers. After Back-End-of-Line (BEOL) process is completed, a device wafer runs through a planarization process and is bonded with a carrier wafer. The bonded wafer is then mechanically and chemically thinned down from the bottom side of the device wafer to the target thickness. The new backside Si surface is implanted with a shallow P+ layer followed by laser anneal for dopant activation. Backside antireflection (BARC) layers are coated to further enhance optical sensitivity. Pad opening, color filter array, and packaging process are performed to complete the BSI sensor manufacturing.The aforementioned process utilizes several new tools uncommon to traditional CMOS technology and that poses certain challenges in the process development. The major steps are wafer bonding, thin-down process, and laser anneal. Wafer bonding mainly determines the maximum mechanical stress the BSI wafers can tolerate in following processes including thermal treatment and packaging. It also imposes a certain stress to the bonded device and carrier wafers. Bond voids at the bonding interface and wafer distortion are key parameters of the bonding process. Fig. 2 shows a bonding process window obtained to achieve voidfree and good distortion. Optimized with a bond anneal process, 300mm wafers have been proven to withstand complete BSI process, color filter array (CFA), and packaging.For wafer thin-down process, f...

Hydrogen plasmas generated by electron cyclotron resonance currently provide the most efficient plasma exposure technique available for passivating the grain boundaries of polycrystalline silicon. In this report, we show that careful optimization may be required when using this passivation approach on polycrystalline silicon gated, polycrystalline silicon thin film transistors fabricated using low temperature oxides. Optimization is found to be necessary for thin film transistors (TFTs) with polycrystalline Si gates in order to prevent the onset of high leakage currents which can develop when exposures are too long. The effects of exposure time, substrate temperature, microwave power level, pressure, and plasma dilution with an inert gas are examined to determine the conditions for optimal improvement in electrical performance. A model is also presented to explain this need for optimization of the electron cyclotron resonance hydrogen plasma passivation of poly-Si TFTs.

Articles you may be interested inAnnealing effects on the electrical properties and microscopic structure of semiinsulating polycrystalline silicon films J. Appl. Phys. 75, 7916 (1994); 10.1063/1.356578Physical properties of semiinsulating polycrystalline silicon. I. Structure, electronic properties, and electrical conductivityThe influence of an oxidizing ambient on the structure and electrical characteristics of thin films of semi-insulating polysilicon (SIPOS) has been studied. It is shown that SIPOS films 135 nm thick can be completely oxidized to amorphous silicon dioxide after 24 h at 600°C in wet oxygen. The midgap interface state density after oxidation and postmetallization anneal is 4 X 1010 em -2 e V-I. We also show that this material is suitable for use as a low-temperature deposited gate dielectric for polycrystalline thin-film transistors.

The electrical and optical properties of Indium-Tin-Oxide (ITO) films, deposited by radio frequency (r.f.) magnetron sputtering, were studied. ITO films, when deposited using optimum sputtering conditions, were reproducibly prepared with resistivity as low as 1.5 × 10−4 Ω-cm and optical transmissivity higher than 80% over the wavelength range of interest. Device stability when ITO is used as a replacement for polysilicon as a gate electrode in silicon charge-coupled device (CCD) image sensors was also studied. After an anneal process at 950 °C in N2 the device degraded. The degradation can be attributed to the generation of oxide charge and interface states in the ITO/SiO2/Si system.