A linear time algorithm for timing directed circuit optimizations

Agarwala, S.; Bosshart, P.

doi:10.1109/iscas.1994.408793

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…The updation of source representation consists of nding the (nand ..) ((nor ..)) and (not ..) sub-expressions, and replacing the nand (nor) with an and (or) and the not with a wire. The timing analysis tool [3] computes the longest and the shortest timing paths in the circuit by computing the same through each gate using two breadthrst traversals of the circuit. During the traversals, two timing directed optimizations namely, gate-input reordering and conversion back to CMOS are carried out.…”

Section: Inverter Collapsingmentioning

confidence: 99%

A system for incremental synthesis to gate-level and reoptimization following RTL design changes

Prasad

Anirudhan

Bosshart

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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W e address the problem of long cycle time associated with the basic method of optimizing VLSI circuits. W e are developing a system which makes it possible to carry out arbitrary changes to Register Transfer Level (RTL) source description of the circuit after a gatelevel implementation has been synthesized. The system incrementally updates the gate-level implementation. For typical changes this updation produces comparable results but requires only a small fraction of the time for a complete resynthesis. The system makes use of two object representations. W e describe these representations, the maintenance of consistency between them and the incremental synthesis and reoptimization process. Status of the ongoing research on this system is presented.

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Section: Inverter Collapsingmentioning

confidence: 99%

A system for incremental synthesis to gate-level and reoptimization following RTL design changes

Prasad

Anirudhan

Bosshart

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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“…Our algorithm is based upon the algorithm described in [5]. Each pass of our multi-pass algorithm processes the entire circuit performing the tasks of Mael, Mpar and Mupd in overall linear time.…”

Section: Introductionmentioning

confidence: 99%

Circuit optimization for minimisation of power consumption under delay constraint

Prasad

Roy²

Proceedings of the 8th International Conference on VLSI Design

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We address the problem of optimization of VLSI circuits to minimize power consumption while meeting performance goals. We present a method of estimating power consumption of a basic or complex CMOS gate which takes the internal capacitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. We describe a multipass algorithm which makes use of transistor reordering to optimize performance and power consumption of circuits and which has a linear time complexity per pass. The algorithm has been benchmarked on several large examples and the results are presented.

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A linear time algorithm for timing directed circuit optimizations

Cited by 2 publications

References 8 publications

A system for incremental synthesis to gate-level and reoptimization following RTL design changes

A system for incremental synthesis to gate-level and reoptimization following RTL design changes

Circuit optimization for minimisation of power consumption under delay constraint

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