A Low-cost Fault Tolerance Method for ARM and RISC-V Microprocessor-based Systems using Temporal Redundancy and Approximate Computing through Simplified Iterations

Abstract

Approximate Computing techniques have been successfully used to reduce the overhead associated with redundancy in fault-tolerant system designs. This paper presents a fault tolerance method to reduce the execution time overhead of the well-known Time Redundancy technique by means of an improvement proposed for the Approximate Computing software-based technique known as loop perforation. Time Redundancy is a software-based fault tolerance technique that involves executing replicas of a task at different times. We propose to approximate the tasks to be executed using a new approximate computing technique based on loop perforation, i.e., simplified iterations. The novelty of this method is the combined use of the fault tolerance technique, temporal redundancy, jointly with the new proposed Approximate Computing technique, simplified iterations. The proposal is validated through simulation-based fault injection campaigns on several test programs for the ARM and RISC-V microprocessor architectures. Experimental results verified not only the applicability of the proposal in different architectures, but also its effectiveness, showing a good trade-off between reliability, error and overhead. Results showed that using the proposed method, a normalized mean work to failure (MWTF) up to 5.28× was obtained with approximation errors lower than those obtained using the traditional loop perforation technique.

Enhancing Fault Tolerance in High-Performance Computing: A real hardware case study on a RISC-V Vector Processing Unit

“…In spatial redundancy approaches, the same computation is executed on multiple hardware resources, possibly implementing a Double Modular Redundancy (DMR) or Triple Modular Redundancy (TMR) [23]. In temporal redundancy approaches, the task execution is replicated in time [24] on the same hardware resource. In the context of highly parallel HPC workloads, if we assume a fixed amount of available hardware resources both approaches come at the cost of increased execution time, since spatial redundancy sacrifices part of the parallelism of the machine.…”

“…Of course, this does not prevent the functional unit busy time to be doubled. Authors in [24] address task-level replication, approximating the task before it is replicated, thus combining approximate computing techniques with temporal redundancy. The execution time overhead is reduced thanks to the approximate version of the original task being re-executed.…”