A Low-Cost Jitter Measurement Technique for BIST Applications

Huang, Jiun-Lang; Huang, Jong Shin; Liu, Yuan-Shuang

doi:10.1007/s10836-006-8600-0

Cited by 15 publications

(30 citation statements)

References 12 publications

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“…The data stream of the beat signal can be used to estimate the CDF of the HF jitter, and this function can be used thereafter to estimate the RMS value of the random Gaussian jitter. This technique for HF jitter estimation has been presented and used in several previous works [7][8][13][14][15]. It must be noticed that the assumption of Gaussian HF jitter is widely accepted by industry since there is no evidence of non-Gaussian HF jitter in actual circuits.…”

Section: Under-sampling Conceptmentioning

confidence: 99%

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High frequency jitter estimator for SoCs

Gall

Alhakim

Valka

et al. 2015

2015 20th IEEE European Test Symposium (ETS)

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This paper presents an Embedded Test Instrument (ETI) for the estimation of the High Frequency (HF) jitter of an observed clock signal. The ETI uses a second reference clock for under-sampling the observed signal similar to previous approaches. However, the analysis of the test response does not require the construction of the Cumulative Distributed Function (CDF) of the jitter as in previous approaches. Instead, the HF jitter of the input observed signal is transformed at the output of the ETI into a digital value that corresponds to a number of unwanted signal transitions. We demonstrate in this paper that the transfer function of the ETI defined by the ratio of the number of unwanted signal transitions and the input HF jitter is linear. This property leads to a simple circuit implementation. The linearity of the ETI is demonstrated firstly by behavioral simulation, using a theoretical model of the output of the undersampling process, and secondly by transistor-level simulation using the 65 nm CMOS bulk technology by ST Microelectronics.We also present experimental measurements that have been carried out using an FPGA-based test platform to validate the linearity of the transfer function in the presence of non-idealities that can affect the ETI. Finally, we demonstrate the exploitation of the ETI within Systems-on-Chip (SoCs) produced in highvolume by ST Microelectronics.

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Section: Under-sampling Conceptmentioning

confidence: 99%

“…The use of signal under-sampling for HF jitter estimation has been considered by several works [7][8][13][14][15]. In this case, the TDC is replaced by a simple latch and the resolution of the measurement is defined by the difference between the period of the observed and the strobe signal.…”

Section: Introductionmentioning

confidence: 99%

High frequency jitter estimator for SoCs

Gall

Alhakim

Valka

et al. 2015

2015 20th IEEE European Test Symposium (ETS)

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“…2(a). Consisting of a variable delay line and a phase comparator, it was previously adopted by [11,2,15,3]. The phase comparator determines the phase relationship (lead or lag) between the rising edges of SU T (the signal under test) and SU T (the delayed SU T ).…”

Section: Period Comparisonmentioning

confidence: 99%

A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter

Huang

2006

2006 15th Asian Test Symposium

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In this paper, a random jitter (RJ) extraction technique in the presence of sinusoidal jitter (SJ) is proposed for onchip jitter tolerance testing applications. First, the periodtracking technique [4] is utilized to derive the SJ frequency and amplitude information. Then, using the same designfor-test (DfT) circuitry, samples from the total jitter cumulative distribution function (CDF) are taken. From the SJ information and CDF samples, a binary search method is utilized to obtain the RJ sigma value. The features of the proposed technique include low delay line resolution requirement and high process variation tolerance. Simulation results are performed and shown to validate the proposed technique.

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“…Buffering and matching for testing RF circuits is common not only in VCO testing, but also in testing other blocks, such as low noise amplifiers (LNA) [8]. All the above techniques fall in the category of functional tests and are aimed at testing the frequency of oscillation [9] or timing jitter [10] of oscillators. Structural tests aimed at finding physical defects in GHz oscillators have also been recently reported in [11].…”

Section: Introductionmentioning

confidence: 99%

A Time-Based Technique for Testing LC-Tank Oscillators

Safi-Harb

Mirabbasi

2012

IEEE Trans. Circuits Syst. I

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This paper describes a new architecture that explores time-based signal-processing concepts for testing LC-tank radiofrequency (RF) oscillator circuits, and in particular, quadrature oscillators, while relying on low-frequency digital test equipment. The proposed system has two inputs that are two step-like signals with a time separation that is externally controlled. The output of the system is an amplified and digitized time separation that is a function of the time separation between the applied input steps and the oscillator output frequency characteristics. Coarse time digitization circuits are used to read the output, from which the frequency of oscillation of the oscillator is deduced. A proof-ofconcept circuit is designed and fabricated in a standard 0.18-m CMOS process. Experimental results confirm the feasibility of the proposed approach, which is demonstrated in this work with the successful on-chip measurement of 1.5 and 1.7 GHz oscillation frequencies.

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A Low-Cost Jitter Measurement Technique for BIST Applications

Cited by 15 publications

References 12 publications

High frequency jitter estimator for SoCs

High frequency jitter estimator for SoCs

A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter

A Time-Based Technique for Testing LC-Tank Oscillators

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