A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

Li, Di; Yang, Yong; Shi, Zuochen; Liu, Yang

doi:10.1016/j.mejo.2014.10.004

Cited by 2 publications

(2 citation statements)

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“…One of the most attractive solutions is the DEM technique due to its cost‐effectiveness and simplicity. In fact, the DEM is a digital SDM which moves the mismatch errors to high frequency by controlling the selection of DAC unit elements . In this work, third‐order DEM is adopted to achieve excellent mismatch noise suppression.…”

Section: Circuit Designmentioning

confidence: 99%

“…In fact, the DEM is a digital SDM which moves the mismatch errors to high frequency by controlling the selection of DAC unit elements. 30,31 In this work, third-order DEM is adopted to achieve excellent mismatch noise suppression. Firstly, the conventional binary weighted capacitors (C s , 2C s , …, 16C s ) are firstly replaced by unit elements (C unit ) array, as shown in Figure 4, so that the elements are independent with each other and can be selected under the control of DEM algorithm.…”

Section: Circuit Designmentioning

confidence: 99%

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A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

Fei

Zhang

et al. 2019

Circuit Theory & Apps

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Summary A high SNDR discrete‐time (DT) 2‐1 MASH sigma‐delta modulator (SDM) for 15‐MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five‐bit flash quantizer was adopted in both stages to improve the overall signal‐to‐noise and distortion ratio (SNDR) performance, and third‐order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18‐μm CMOS technology, the occupied area of the modulator was 0.24 mm2 and dissipation power 25.4 mW from a 1.8‐V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15‐MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious‐free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5‐dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15‐MHz bandwidth. A 15‐MHz bandwidth multibit MASH2‐1 discrete‐time sigma‐delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High‐order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18‐μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15‐MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high‐frequency biomedical imaging or sensing systems, and so on.

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Section: Circuit Designmentioning

confidence: 99%

Section: Circuit Designmentioning

confidence: 99%

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

Fei

Zhang

et al. 2019

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

show abstract

A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC

Chen

2018

Circuits Syst Signal Process

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A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

Cited by 2 publications

References 27 publications

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC

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A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

Cited by 2 publications

References 27 publications

A 15‐MHz bandwidth double sampling MASH25b‐15b sigma‐delta modulator with DEM for multibit DACs

A 15‐MHz bandwidth double sampling MASH25b‐15b sigma‐delta modulator with DEM for multibit DACs

A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC

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A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs