A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop

Abstract

This paper introduces a pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 m integrated circuit with active area of 0.4 mm 2 and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), 63.9 dBc, and 200 fs (peak-to-peak), respectively.

A 285-fsrmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

“…Nonetheless, the design of the pulse generator (PG) producing the suitable injection pulse is challenging [2]. As an alternative to the use of the PG, a complementary switch (CS) injection technique can be employed [7].…”

“…The key concept of detecting f ERR in [2] is based on the phenomenon that the pulse-width difference is proportional to f ERR when the reference clock is injected into the oscillator. By comparing the two pulse widths, f ERR can be detected and compensated.…”

“…Second, the injection lock range f LR becomes narrow for a large multiplication factor N. In other words, achieving low jitter becomes more challenging as N increases. To detect this frequency mismatch, a fine resolution time-to-digital converter (TDC) is employed in [2] at the cost of increased power consumption. In addition, using a phase detector (PD) with a replica delay cell, as proposed in [3], suffers from the problem of device mismatches.…”

“…In addition, using a phase detector (PD) with a replica delay cell, as proposed in [3], suffers from the problem of device mismatches. Moreover, the absence of startup circuits in [2] and [3] requires the oscillation frequency to be set within the injection lock range initially. [1] and [3] achieve an excellent figure-of-merits (FoMs) of less than -240 dB with a small N since achieving the high performance in ILOs is challenging with a higher N [4].…”

A wideband injection locking scheme and quadrature phase generation in 65nm CMOS

“…11(a)] for three reference frequencies (14,15,and 16 GHz), and an average JTB of 400 MHz was recorded. High JTB helps in retaining the low-frequency jitter while eliminating high-frequency jitter, as depicted in Fig.…”