A Low Leakage SRAM Macro With Replica Cell Biasing Scheme

Takeyama, Y.; Okada, H.; Hirabayashi, O.; Kushida, K.; Otsuka, N.

doi:10.1109/jssc.2006.870763

Cited by 32 publications

(18 citation statements)

References 7 publications

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“…Given the results in Figure 1 and recent work such as [2,8,9,12,17,24], peripheral circuits are equally if not more important to address in a cache.…”

Section: Figure 2 (A) Stacking Sleep Transistor To Reduce Leakage (Bmentioning

confidence: 75%

“…Device scaling leads to threshold voltage fluctuation, which makes the cell bias control difficult to achieve. In response, [8] proposed a Replica Cell Biasing scheme in which the cell bias is not affected by Vdd and Vth of peripheral transistors. [14,31] proposed a forward body biasing scheme (FBB) in which the leakage power is suppressed in the unselected memory cells of cache by utilizing super Vt devices.…”

Section: Circuit-level Leakage Controlmentioning

confidence: 99%

“…A number of process and circuit techniques have been proposed to significantly reduce leakage of the memory cell array making SRAM peripheral circuits the main sources of leakage. Recent results have shown that a considerable amount of leakage occurs in the peripheral SRAM circuits, such as decoders, word-line and output drivers, etc [2,8,9,12,17,24]. Figure 1 shows leakage components for different size SRAMs in 65nm technology (based on CACTI 5.1 [22]), with peripheral circuits -data drivers, address driver, decoder and wordline drivers -accounting for over 80% of overall SRAM leakage.…”

Section: Introductionmentioning

confidence: 99%

“…The reason is the use of larger, faster and more leaky transistors in peripheral circuits to satisfy timing requirements, while smaller and less leaky transistors are used in memory cells. In fact, SRAM memory cells can be optimized for low leakage currents without a significant impact on the cell area or performance [8,12,24]. This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processors.…”

Section: Introductionmentioning

confidence: 99%

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Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Homayoun

Makhzan

Veidenbaum

2008

Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral circuits, which according to recent studies account for a considerable amount of cache leakage. At circuit level, we propose a novel design with multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and wakeup delay. Architectural control is proposed to decide "when and how" to use these different low-leakage modes using cache miss information to guide its action. This control is based on simple state machines that do not impact area or power consumption and can thus be used even in the resource constrained processors. Experimental results indicate that proposed techniques can keep the L1 cache peripherals in one of the low-power modes for more than 85% of total execution time, on average. This translates to an average leakage power reduction of 50% for 65nm technology. The DL1 cache energy-delay product is reduced, on average, by 20%.

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“…Given the results in Figure 1 and recent work such as [2,8,9,12,17,24], peripheral circuits are equally if not more important to address in a cache.…”

Section: Figure 2 (A) Stacking Sleep Transistor To Reduce Leakage (Bmentioning

confidence: 75%

Section: Circuit-level Leakage Controlmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Homayoun

Makhzan

Veidenbaum

2008

Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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show abstract

“…The performance of SRAM would deteriorate as the bit-line leakage increases, and the read operation would even fail when the amount of leakage reaches a critical value [8,9,10,11]. To combat the adverse effect caused by the bit-line leakage, several methods and techniques have been proposed in [12,13,14,15,16].…”

Section: Introductionmentioning

confidence: 99%

Additive-calibration scheme for leakage compensation of low voltage SRAM

Peng

Lin

et al. 2016

IEICE Electron. Express

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As the bit-line leakage increases, the performance of SRAM will decline. Especially, the read operation will even fail when the amount of the leakage reaches a critical value. In this paper, we present a new technique, called Additive Calibration (AC), which can combat the bit-line leakage problem even in low voltage. Simulation results show that the maximum tolerant bit-line leakage current of our AC scheme is increased by 45.6% compared with the previous X-calibration scheme. Thus, this method can perform at higher frequency with much lower power consumption.

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Dynamic and Adaptive Techniques in SRAM Design

Wuu

2008

Adaptive Techniques for Dynamic Processor Optimization

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A Low Leakage SRAM Macro With Replica Cell Biasing Scheme

Cited by 32 publications

References 7 publications

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Additive-calibration scheme for leakage compensation of low voltage SRAM

Dynamic and Adaptive Techniques in SRAM Design

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