A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating

Själander, Magnus; Drazdziulis, Mindaugas; Larsson-Edefors, Per; Eriksson, Henrik

doi:10.1109/iscas.2005.1464922

Cited by 19 publications

(6 citation statements)

References 1 publication

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“…We first look at one representative coarse-grain power gating technique, a twin-precision multiplier [30], which is nearly directly comparable with our results, thanks to the same size process (130nm) and similar driving voltages (our 1.3V vs. their 1.2V). There are several differences between our two approaches: Sjalander et al's circuit is based on a tree multiplier, while ours is a simpler array multiplier; their approach allows for only two different precisions to be used, whereas our design offers a continuum of operating precisions.…”

Section: Comparison With Other Techniquessupporting

confidence: 64%

“…have proposed a scheme in which energy can be traded for quality, similar to prior work [1], in a DCT algorithm using only three -tradeoff levels‖ [28]. Other research by Usami et al [29] and Sjalander et al [30] has led to variable-precision power-gated multipliers, which will save leakage current in smaller processes. However, both of these papers only allow for two different operating precisions, while our approach provides a full range of possible precisions, adaptable to the intended circuit application.…”

Section: Circuit Designs For Low Powermentioning

confidence: 99%

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Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units

Pool¹,

Lastra²,

Singh³

2011

Journal of Low Power Electronics

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In mobile devices, limiting the Graphics Processing Unit's (GPU's) energy usage is of great importance to extending battery life. This work shows that significant energy savings can be obtained by reducing the precision of graphics computations, yet maintaining acceptable quality of the final rendered image. In particular, we focus on a portion of a typical graphics processor pipeline-the vertex transformation stage-and evaluate the tradeoff between energy efficiency and image fidelity. We first develop circuit-level designs of arithmetic components whose precision can be varied dynamically with fine-grained power gating techniques. Spice simulation is used to characterize each component's energy consumption, based on which a system-level energy model for the entire vertex stage is developed. We then use this energy model in conjunction with a graphics hardware simulator to determine the energy savings for real workloads. Results show that, solely by changing the precision of the arithmetic in the vertex shaders' ALUs, we can save up to 10% of the overall energy in the GPU. As promising as these savings are, we expect that our circuits and approach will enable energy-precision tradeoffs in other areas of the graphics pipeline, such as the pixel shader, which consume even more energy than the vertex shader.

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Section: Comparison With Other Techniquessupporting

confidence: 64%

Section: Circuit Designs For Low Powermentioning

confidence: 99%

Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units

Pool¹,

Lastra²,

Singh³

2011

Journal of Low Power Electronics

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“…Power-gating has already been applied to twin-precision (e.g 32 and 16 bit operands) multipliers [8], [9].…”

Section: Programmable Truncated Multipliermentioning

confidence: 99%

“…The truncated bits in the multipliers (k = 0, 4,8) can be programmed by controlling the power-gating on-the- fly, although the transition 'on-off' (and 'off-on') requires two clock cycles as explained in Sec. III.…”

Section: Case Study: Fir Filtermentioning

confidence: 99%

Truncated multipliers through power-gating for degrading precision arithmetic

Albicocco

Cardarilli

Nannarelli

et al. 2013

2013 Asilomar Conference on Signals, Systems and Computers

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When reducing the power dissipation of resource constrained electronic systems is a priority, some precision can be traded-off for lower power consumption. In signal processing, it is possible to have an acceptable quality of the signal even introducing some errors. In this work, we apply power-gating to multipliers to obtain a programmable truncated multiplier. The method consists in disabling the least-significant columns of the multiplier by power-gating logic in the partial products generation and accumulation array. © 2013 IEEE

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“…Based on earlier studies [23], [24] where the foundation of the techniques was laid, the use of power gating to reduce leakage power for narrow-width operands in integer arithmetic was comprehensively evaluated using an automated design flow for power gating [25]. Among the results from experiments in a 45-nm process technology, power gating of a 32-bit multiplier is demonstrated to yield an 11.6x static leakage energy reduction per 8x8-bit operation, at a performance penalty of 6.7%.…”

Section: Power Gating Of Idle Circuitsmentioning

confidence: 99%

FlexCore: Implementing an exposed datapath processor

Själander

Larsson-Edefors

2013

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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The FlexCore processor is the resulting implementation of an exposed datapath approach conceptualized in the FlexSoC programme. By way of a crossbar switch interconnect, all execution units in a FlexCore datapath can potentially communicate, allowing the inherent hardware parallelism to be utilized. This interconnect enables configuration of a datapath to match an application domain, for example, by way of datapath accelerators. The baseline FlexCore is a general-purpose processor (GPP) and since all FlexCore configurations are extensions to the baseline, they offer GPP functionality as complement to the domain-specific functionality. This paper gives an overview of the implementation of complete FlexCore processors, accompanied with discussions on datapath interconnects, datapath extensions and instruction decompression.

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A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating

Cited by 19 publications

References 1 publication

Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units

Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units

Truncated multipliers through power-gating for degrading precision arithmetic

FlexCore: Implementing an exposed datapath processor

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