Truncated multipliers through power-gating for degrading precision arithmetic

Abstract

When reducing the power dissipation of resource constrained electronic systems is a priority, some precision can be traded-off for lower power consumption. In signal processing, it is possible to have an acceptable quality of the signal even introducing some errors. In this work, we apply power-gating to multipliers to obtain a programmable truncated multiplier. The method consists in disabling the least-significant columns of the multiplier by power-gating logic in the partial products generation and accumulation array. © 2013 IEEE

Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors

“…Albicocco et al [2] leverage sleep transistor insertion to select between accurate and approximate modes by using power gating. The error introduced by truncation is not compensated in any way, producing an average error larger than other works.…”

“…As an example, operations affecting control flow, such as computation of loop indices, must be executed accurately to avoid semantic errors. A possible solution to this problem is to implement hybrid units, in which truncated arithmetic is implemented using power gating [2]. In this way, the same circuit may implement accurate or approximate operations by switching power supply at the gate level, and rerouting signals appropriately through multiplexers.…”