Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors

Osorio, Roberto R.; Rodriguez, Giovanna

doi:10.1109/access.2019.2913743

Cited by 21 publications

(10 citation statements)

References 21 publications

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“…Two-dimensional discrete cosine transform (DCT) is a widely used technique for lossy image compression. DCT transforms the image from the spatial domain to the frequency domain, where the high-frequency DCT coefficients are selectively discarded to allow for efficient compression [54,55].…”

Section: Lossy Image Compressionmentioning

confidence: 99%

A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing

2021

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Multiplication is an essential image processing operation commonly implemented in hardware DSP cores. To improve DSP cores’ area, speed, or energy efficiency, we can approximate multiplication. We present an approximate multiplier that generates two partial products using hybrid radix-4 and logarithmic encoding of the input operands. It uses the exact radix-4 encoding to generate the partial product from the three most significant bits and the logarithmic approximation with mantissa trimming to approximate the partial product from the remaining least-significant bits. The proposed multiplier fills the gap between highly accurate approximate non-logarithmic multipliers with a complex design and less accurate approximate logarithmic multipliers with a more straightforward design. We evaluated the multiplier’s efficiency in terms of error, energy (power-delay-product) and area utilisation using NanGate 45 nm. The experimental results show that the proposed multiplier exhibits good area utilisation and energy consumption and behaves well in image processing applications.

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Section: Lossy Image Compressionmentioning

confidence: 99%

A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing

2021

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“…However, such CGRAs suffer from high area, stems from multiple datapath in PEs. Amortizing this penalty, few works have narrowed their focus to design approximate SIMD Mul and/or Div [15], [19].…”

Section: Related Workmentioning

confidence: 99%

BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge

Ebrahimi

Kumar

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Coarse Grained Reconfigurable Architectures (CGRAs) have proved to be viable platforms for health monitoring applications. Targeting energy-efficiency, state-of-the-art (SoA) CGRAs are augmented with approximation techniques, while still maintain acceptable accuracy at final Quality of Result (QoR). However, such CGRAs suffer from overheads of collecting separate Add/Mul/Div units. We propose BioCare as an area-and energy-efficient CGRA for health-monitoring edge devices, which exploits the synergistic effects of multiple approximations across HW/SW stack. BioCare offers different levels of energy-accuracy trade-off through the plasticity of its small PEs, each can support precision-adaptability with a Single Instruction, Multiple Data (SIMD) manner. BioCare demonstrates its superiority over SoAs, by achieving up to 32% and 67% area-and energy-savings, with 3.6× higher throughput. In addition to analysis on multiple kernels, evaluations on a multi-kernel ECG application shows that BioCare speed-ups the QRS detection latency by 61%, with 0% loss in accuracy. Our implementations will be available at

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“…Thus, the HW behavior of all designs in Tables X and XI can be synchronized to the accuracy results shown in Tables VIII and IX. Moreover, according to [24], [32], and [44], the bias function for [32] in Tables X and XI was structured using a general sorting circuit based on [24] to avoid the addition of negative digit values. The comparison results show that the non-TEC-based PT and DT methods require the highest and lowest HW costs, respectively, which are rational to their accuracy performances.…”

Section: B Hardware Performance Comparisonsmentioning

confidence: 99%

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

Tang

Han

2020

IEEE Access

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This paper presents a multiply-accumulate (MAC) unit that enables a dual-mode truncation error compensation (TEC) scheme based on a fixed-width Booth multiplier (FWBM) for convolutional neural network (CNN) inference operations. The proposed tailored TEC schemes of Modes 1 and 2 can achieve high MAC accuracy for a general or rectified linear unit-based CNN model with general (Mode 1) or positive/zero (Mode 2) input patterns. By pre-calculating the pre-known CNN model coefficients, the proposed dual-mode TEC scheme can be realized using minimal partial product operations with high hardware efficiency using a software-hardware codesign approach. Further, a reconfigurable architecture of the resultant MAC unit is presented to realize the proposed dual-mode TEC scheme. By evaluating the accuracy for 9-N and 25-N MAC operations (N denotes the number of times MAC is performed), a MAC operation using the proposed TEC scheme can achieve the highest accuracy for Modes 1 and 2, relative to contrast samples that directly employ the FWBM with a conventional TEC function. The hardware performances of 9-N and 25-N MAC units are also evaluated using the TSMC 40-nm standard cell library. Compared with the contrast TEC-enabled designs, the proposed MAC unit exhibits higher hardware efficiency in terms of area, delay, and power consumption and achieves a minimum reduction of more than 40% in both area-delay-error and power-delay-error products. Moreover, the resultant 9-N and 25-N MAC units are verified using a system-on-chip field-programmable gate array platform to test a CNN model for handwritten digit classification.

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Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors

Cited by 21 publications

References 21 publications

A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing

A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing

BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

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