A Low Multiplier and Multiplication Costs 256-point FFT Implementation with Simplified Radix-24 SDF Architecture

Abstract

In this paper, we propose a low multiplier and multiplication complexities 256-point fast Fourier transform (FFT) architecture, especially for WiMAX 802.16a systems. Based on the radix-16 FFT algorithm, the proposed FFT architecture utilizes cascaded simplified radix-24 single-path delay feedback (SDF) structures. The control circuit of the proposed simplified radix-24 SDF FFT architecture is simple.The hardware requirement of the proposed FFT architecture only needs 1 complex multiplier and 56 complex adders for supporting 256-point computations.The computation complexity of multiplications and the hardware complexity of the proposed FFT architecture need less complexity than both complexities of the previous FFT structures in 256-point FFT applications. In hardware verifications, the output throughput rate of our FFT design processes up to 35.5M samples/sec with Xilinx Virtex2 1500 FPGA, and it processes up to 51.5M samples/sec with UIMC 0.18gm standard cell technology. The throughput rate of this implementation is suitable for WiMLAX 802.16a application, whose maximum sample rate is 32MHz.

Calculation of computational complexity for radix-2 p fast fourier transform algorithms for medical signals

“…These algorithms were introduced with radix-2 2 in 1996[2] and are developing for higher radices. [3456789] Using radix-2 p to calculate FFT for real signals like medical signals is very efficient. [10]…”

The Serial Commutator FFT

“…The proposed architecture improves the clock frequency of previous designs. At the same time it achieves less area than previous 2048-point [16] and 256-point [17] SDF FFTs, high SQNR and low power consumption. In the table, area and power are normalized to 55 nm and 0.9 V according to [18].…”

Implementation of fast FFT design for 128-point using Radix-22 CFA

“…The proposed FFT design, common factor algorithm based on Radix-2 2 , 2-point DFT butterfly, trivial circuit are described under this section for 128-point FFT. The DFT is to compute the X(k) sequence of complex-valued numbers N given another sequence of data x(n) of length N, expressed as [4]:…”

“…(− ) 2 1 and 128 3 ( 1 +2 2 ) are processing factor (PF). The structure of the proposed design for 128-point is shown in figure 2 that retains seven numbers of FFT stages -FS 1 , FS 2 , FS 3 , FS 4 , FS 5 , FS 6 , FS 7 and shift registers -SR 1 , SR 2 , SR 3 , SR 4 using n 3 , k 1 , and k 2 values. The trivial circuit in case of − multiplication, inverts the sign of real part of a complex number then swaps inverted real part and imaginary part of a complex number.…”