A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier

Abstract

This paper presents a new low offset comparator with a mismatch-suppressed dynamic preamplifier Various mismatches contribute to comparators's input referred offset. The proposed mismatch suppression is achieved by sampling the mismatches at the dynamic preamplifier's output node during the precharge phase. A time-domain analysis method is utilized to quantize the suppression effects. By the techniques, a 1-GS/s fourinput comparator is implemented by 65-nm CMOS technology. It achieves a 60-µW power dissipation and a 1.89-mV 1-sigma(σ) offset voltage, which is a 90% improvement compared to its nonsuppressed counterparts.

A digital phase‐based on‐fly offset compensation method for decision feedback equalisers

“…Furthermore, the works presented in [2,[9][10][11] calibrate offset using digital algorithms at the back-end during regular operation, and offset sampling techniques based on setting V CM at comparator input. Back-end routines increase complexity and thus area and power, while traditional offset sampling methods add loading to the signal path.…”